This is a SG2002 microcontroller, it has 256MB RAM, it has 700Mhz RiscV core and either a 1Ghz RiscV core or a 1Ghz Arm Cortex A53 core, a 25 to 300Mhz 8051 core and a 1 TOPS Tensor unit (TPU). The Ant64 will operate it in RiscV mode. Audio will also go directly from/to the “Jazz” chip.
.The TF card interface (SPI0?) will go to the DeMon chip, which will act as an SD card emulator.
SD1 will go direct to...
Pins 21 to 27 (can be configured as a QSPI NOR Flash interface – they will go direct to the Razz. This way the CPU can communicate with the Razz “gpu” as if it was memory mapped IO.
The SG2002 provides a 100MBPS network port.
The SG2002 has a fast USB interface.
Slower interfaces will go to the Debug monitor, input controller, audio synthesizer and optional “Network controller”.
The current plan is to have the 700Mhz RiscV core provide the operating system, housekeeping tasks, the “monitor” and the built-in computer languages (BASIC/Action). The 1Ghz RiscV core will provide emulation of various processors to simulate various 8 and 16 bit systems.
When emulating a computer, for example an Amiga A1200. The memory inside the SG2002 will be used rather than memory available to the "Razz" chip.
An amiga A1200 has a max memory bandwidth of 28MBytes/sec = 224mbits/sec (a normal amiga is 7Mbytes/sec = 56mbit/sec). With RAM being available to the emulated CPU all the time, it will mean the cpu will emulate as fast as possible.
The simulated GPU in the FPGA will request memory via the SG2002 MIPI RX port – which can operate at up to 1.5Gbit/sec and then transmit the requested data through the MIPI TX port – which can operate at up to 2.5Gbit.
There will be a protocol to read from “chip registers” contained in the FPGA by requesting them from the TX port and waiting for them at the RX port.
Start address | End address | Size | Description |
---|---|---|---|
0000000 | 03FFFFF | 0400000 | 4MB SRAM |
0400000 | 07FFFFF | 0400000 | Reserved |
0800000 | 0FFFFFF | 0C00000 | Reserved |
8000000 | FFFFFFF | 8000000 | 128MB SDRAM |
Pin | CPU pin | Description | Function | Pin | CPU pin | Description | Function |
---|---|---|---|---|---|---|---|
1 | 19 | GP A17 | RX0 from DeMon | 28 | 26 | GP A19 | JTAG TCK |
2 | 18 | GP A16 | TX0 to Jazz | 27 | 27 | GP A18 | JTAG TMS |
3 | GND | 26 | GND | ||||
4 | 17 | GP A15 | VSync | 25 | 29 | GP A29 | JTAG TDO |
5 | VON | 24 | 59 | GP B3/ADC1 | HSync | ||
6 | VOP | 23 | 28 | GP A28 | JTAG TDI | ||
7 | 25 | GP A24 | FRAM CS | 22 | 51 | GP P18 | SPI2 CTRL0 |
8 | 24 | GP A23 | FRAM MISO | 21 | 52 | GP P19 | SPI2 CTRL1 |
9 | 23 | GP A27 | FRAM WP | 20 | 54 | GP P21 | SPI2 SDI |
10 | 22 | GP A25 | FRAM MOSI | 19 | 55 | GP P22 | SPI2 SDO |
11 | 21 | GP A22 | FRAM SCK | 18 | 56 | GP P23 | SPI2 SCK |
12 | 20 | GP A26 | FRAM HOLD | 17 | 53 | GP P20 | SPI2 SDA |
13 | 5V | 16 | 15 | GP A14 | LED OUT SPI CTRL2 | ||
14 | 5V | 15 | 3V3 |
Value | Selected Device |
---|---|
0 | DeMon0 |
1 | Razz |
2 | Jazz |
3 | SticKey |
4 | |
5 | |
6 | |
7 |
SDCard | CPU pin | Description | Function |
---|---|---|---|
4 | 11 | SDIO0 D2 | |
2 | 12 | SDIO0 D3 | |
3 | 7 | SDIO0 CMD | |
4 | 6 | SDIO0 CLK | |
7 | 8 | SDIO0 D0 | |
8 | 10 | SDIO0 D1 |
Pin | CPU pin | Description |
---|---|---|
USB DP | 69 | USB DP |
USB DM | 70 | USB DM |
SBU2 | 19 (see other chart) | GP A17 (RX0) |
SBU1 | 18 (see other chart) | GP A16 (TX0) |
Pin | CPU pin | Description |
---|---|---|
CAM SDA | 44 | I2C P SDA - DeMon I2C |
CAM SCL | 43 | I2C P SCL - DeMon I2C |
TP0 RST | 41 | I2C P4 |
TP0 INT | 40 | I2C P3 |
Pin | CPU pin | Description |
---|---|---|
PWR PWM | 58 | PWM0/GP B0 |
BL PWM | 49 | PWM10/GP P2 |
Pin | CPU pin | Description | Function |
---|---|---|---|
1 | 62 | EPHY TP | TXP/GP B25 |
2 | 63 | EPHY TN | TXN/GP B24 |
3 | 64 | EPHY RP | RXP/GP B27 |
6 | 65 | EPHY RN | RXN/GP B26 |
9/10 | GND |
Pin | CPU pin | Description | Function |
---|---|---|---|
14 | 84 | MIPI TX2P | video out |
15 | 83 | MIPI TX2N | video out |
17 | 86 | MIPI TX1P | video out |
18 | 85 | MIPI TX1N | video out |
20 | 88 | MIPI TX0P | video out |
21 | 87 | MIPI TX0N | video out |
27 | 47 | LCD0 RESET/GP P0 | Pixel clock |
Pin | CPU pin | Description | Function |
---|---|---|---|
2 | 72 | MIPI RX4N | video in |
3 | 73 | MIPI RX4P | video in |
5 | 74 | MIPI RX3N | video in |
6 | 75 | MIPI RX3P | video in |
8 | 76 | MIPI RX2N | video in |
9 | 77 | MIPI RX2P | video in |
11 | 78 | MIPI RX1N | video in |
12 | 79 | MIPI RX1P | video in |
14* | 80 | MIPI RX0N | video in |
15 | 81 | MIPI RX0P | video in |
17 | 48 | CAM IO0/GP P1 | |
18* | CAM IO1 | ||
20 | 43 | CAM SCL | See touch pinouts |
21 | 44 | CAM SDA | See touch pinouts |
Important: The Ant32 and Ant64 are both still at early design and prototype stage, everything you see here is subject to change.