“DeMon” – Debug + monitor (system controller), pronounced “Demon”

CPU overclocked from (1x) 150Mhz (1.1v) to (2x) 300Mhz (1.2v), possibly to (3x) 460Mhz (1.5v) – other have driven the RP2350B to over 600Mhz (2v).

DeMon has 16MB flash, 8MB PSRAM (GPIO-8), at boot it programs Razz (FPGA), simulate the SD card from the SG2000. FRAM is accessed via GPIO-0.

This will connect to the SWD port of the “QWM” chip and “Jazz” chip. This will allow it to program those components with their firmware (if it needs updating) and provide hardware debugging for any of the components.

Debug streams will also be sent back from each component and then to the “main processing unit”.

It will be able to reset any of the components remotely. The debug monitor will also control the boot state and act as a watchdog for the SG2000 “main processing unit”.

DeMon can act as an SPI slave for the SG2000, it emulates an SD card interface.

The DeMon is actually a RP2350B chip that has connections to the hardware debug ports of the other chips.

USB host for keyboard, mouse, joypad.

The real-time clock chip is the Microchip MCP74910 (64 bytes battery backed SRAM, 128 bytes EEPROM, 8 bytes protected EEPROM, supports 2001 to 2399).

DeMon has 8MB PSRAM available.

The real-time clock chip is the Microchip MCP74910 (64 bytes battery backed SRAM, 128 bytes EEPROM, 8 bytes protected EEPROM, supports 2001 to 2399, cost is less than £1). The battery is a CR2450 as it has much more power than a standard ”coin” battery, can last up to 20 years!

Radio communication

An ESP-C5-WROOM-1-N16R4 chip will be connected to DeMon. This will bring 2.4Ghz/5Ghz Wifi (802.11b/g/n/ax), Thread 1.3, Zigbee 3.0 and Bluetooth 5.3 (LE) and Bluetooth mesh, Remote "debrick".

Debugging will be supported via the Wifi (2.4Ghz, router needed, up to 54mbps), Bluetooth (2mbps) or ESP Now (2.4Ghz/5Ghz, no router needed, 1mbps), or 62.5Mbps over SPI (in practice this may be closer to 10mbps).

Optional Waveshare Core1262 HF LoRa Module (SX1262) for possible LoraWAN or/and Meshtastic use.

An internal micro SD card provides 256GB (default, replaceable) internal storage.

FRAM16 map (000000-FFFFFF)

Start address End address Size Description
0000007FFFFF8000008MB SRAM
800000FFFFFF800000Reserved

Hardware reset button to 3v3
GPIO Function GPIO Function
0FRAM 29PWM 6B – Buzzer, input = read on power on, dpdt toggle (side I has a 9k resistor to gnd and side II has a 9k resistor to 3v)
1SPI0 CSn - JTAG TMS 30Jazz/QMK/Cart/Sticks RUN (hi = on, lo =off)
2SPI0 SCK - JTAG TCK 31Jazz/QMK/Sticks SWD CLK (SM0)
3SPI0 TX/MOSI - JTAG TDO 32Jazz SWD IO
4SPI0 RX/MISO - JTAG TDI to Razz 33QMK SWD IO
5Razz Reconfig 34Sticks UPDI
6Razz Ready 35Sticks interrupt/QMK interrupt
7Razz Done 36Razz interrupt
8PSRAM CSn 37I2C0 interrupt Touch debug
9Handshake - ESP-C5 GPIO10 38LCD + TOUCH RESET
10ESP-C5 EN pin (switch on/off wifi) 39LCD CMD/DATA
11Boot mode ESP-C5 GPIO28 (autoprogram) 40SPI1 SEL0
12TX0 (or PIO UART) ESP-C5 GPIO12 (RX) 41SPI1 SEL1
13RX0 (or PIO UART) ESP-C5 GPIO11 (TX) 42SPI1 SEL2
14TX0 (or PIO UART) – to SG2000 43SPI1 TX/MOSI ESP-C5 GPIO2
15RX0 (or PIO UART) – from Jazz 44SPI1 RX/MISO ESP-C5 GPIO7
16PIO SPI0 Cart RX 45SPI1 CSn – multiplexer CS out
17PIO SPI0 Cart CSn 46SPI1 SCK - touch screen / ESP-C5 GPIO6
18PIO SPI0 Cart SCK 47PWM 11B LED light
19PIO SPI0 Cart TX SWDIOESP32-C5 GPIO26
20SPI0 (SG2000 slave) RX/MOSI SD emulation SWDCLKESP32-C5 GPIO25
21SPI0 (SG2000 slave) CSn ADCREF
22SPI0 (SG2000 slave) SCK 3V3
23SPI0 (SG2000 slave) TX/MISO BOOTSEL
24I2C0 SDA - RTC (67/6f) / Cart SDA/ NFC ($d4,$d5)USB D-Keyboard
25I2C0 SCL - RTC / Cart SCL USB D+(12Mbps)
26Cartridge DETECT (CD) RUN
27RX1 (or PIO UART) Cartridge NFC TX 3V3 EN
28Neopixel data (8 LEDs) VBUS

Using SPI1, and different CSn lines, DeMon controls:

  • A Jazz SPI slave port
  • The ESP32-C5-WROOM-1-N8R4 Wifi subsystem + optional SX1262 lora subsystem
  • A cartridge port (using spi interface – slow, Jazz expansion, etc)
  • The internal micro SD card slot (using spi interface – slow)
  • The keyboard 320x480 touch screen
  • SPI1 CTRL:

    Value Selected Device
    0Sticks
    1QMK
    2Jazz
    3Razz
    4ESP32-C5 GPIO 10
    5Touch TFT
    6Internal micro-SD
    7Cartridge

    ESP32-C5-WROOM-1-N16R4 (v1.2 chip layout)

    Pin Function Pin Function
    1GND 28GND
    23v3 27IO26 - DeMon SWD IO
    3EN - DeMon GPIO12, resistor to gnd 26IO25 - DeMon SWD CLK
    4IO2 - SPI Q/MISO - DeMon GP43 (set to 1 via resistor = 48Mhz crystal) 25IO11 - TX to DeMon RXD
    5IO3 - SX1262 SCK (set to 0 via resistor = 3.3v flash) 24IO12 - RX to DeMon TXD
    6IO0 – SX1262 MOSI (set to vcc via resistor) 23IO23 - NSS
    7IO1 – SX1262 MISO 22NC
    8IO6 SPI CLK - DeMon GP46 21IO15 SX1262 D0 - Input button
    9IO7 SPI ID/MISO - DeMon GP44 20NC
    10IO8 – Handshake - DeMon GP8 19NC (using internal PSRAM)
    11IO9 – SX1262 RF_SW 18IO27 – SX1262 RST
    12IO10 SPI CS0 (IN) DeMon CS 17*IO4 – SX1262 Busy
    13IO13 – SX1262 TX (d6) 16*IO5 – SX1262 DIO1
    14IO12 - SX1262 RX (d7) 15IO28 - (in) auto-program (Demon GPIO11, set to 1 via resistor)
    The ESP32-C5-1-N16R4 has spare connections for a socket for an optional SX1262 (Waveshare Core1262 HF LoRa Module for possible LoraWAN or/and Meshtastic use).

    "Smart cart" cartridge port

    A 30-pin edge connector cartridge port (42mm 2.54 pitch wide) is connected to DeMon. If present, then this is booted in preference to the SD card slot. If a cart is inserted or swapped whilst powered on, the Ant64 will normally automatically be rebooted to it (this can be disabled in options). However, a cartridge can safely be removed whilst powered on and the Ant64 will not reboot, reinserting the same cartridge will also not reboot.

    ABCDEFGHIJKLMNO
    GND3.3vCSRX/MISOSCKTX/MOSICDDeMon ICP SWDCLKDeMon ICP SWDIORESETDeMon SCLDeMon SDAIRQ5vLED
    CRAM WPCRAM HOLDCRAM CSCRAM MISOCRAM SCKCRAM MOSIJazz 0Jazz 1Jazz 2Jazz 3Jazz SCLJazz SDAAudio in LAudio in RGND
    123456789101112131415
    A special NFC "Card cartridge" will have an NFC reader (via I2C with IRQ), a hardware reset, and a MicroSD card slot for game "cache". The NFC card can have the web location or ID of the game and unique serial number, it could transfer the data and do future loads from the Micro SD in the card slot.

    Pins A and 15 on the cartridge will extend further than others. The cartridge has been designed so that a “ROM” cart can be a simple single sided PCB (the letter side), the other side being for enhanced cartridges. The port also allows in-circuit programming of the DeMon chip (the boot system).

    CRAM - Cart memory CS, SCK, HOLD, WP, MISO, MOSI – this is like the FRAM interface, but so we can have smart cartridges that can show cartridge mapped to a memory interface. The lines go to the Razz FPGA. Jazz 0-3 functionality depend on the cartridge, this is set by a configuration EEPROM on the Jazz SDA/SCL lines.

    Neopixels

    No Name Description
    0PowerOff, white during self test, then amber during boot, green when fully booted
    1Internal micro SDNone=off, blue = detected, green = read/write, red = error
    2Cartridge (SD)None=off, blue = detected, green = read/write, red = error
    3Main (fast) SDNone=off, blue = detected, green = read/write, red = error
    4NetworkNone=off, blue = connected, green = read/write, red = error
    5WiFiNone=off, blue = connected, green = read/write, red = error
    6BluetoothNone=off, green = read/write, red = error
    7MidiNone=off, green = read/write, red = error
    The documentation will show the current settings of the LEDs, this way the function can be re-purposed if needed. During self test all the LEDs will be white, each LED will have a different purpose – each changing dependant on if the self test has past or not. Green = passed, Red = failed.

    Antibrick built-in:

    The ESP32 can unbrick DeMon remotely over wifi, or via the ICP cartridge.

    Links

  • JTAG - github.com/kholia/xvc-pico
  • JTAG - github.com/phdussud/pico-dirtyJtag
  • Pico debug - github.com/essele/pico_debug
  • Important: The Ant32 and Ant64 are both still at early design and prototype stage, everything you see here is subject to change.