“Razz” – Raster Engine

This reads a special “display” program to generate the screen layout, from that it will also generate the video signal that is output via HDMI.

It is a GoWin GW5AR FPGA, initially a GW5A in a Tang Primer 25k package.

The Razz chip will have direct access to its own 5ns 64MByte SDRAM, configured as 32M words x 16. This is provided by two Winbond W9825G6KH-5 chips (this could be doubled if needed to 5ns 128Mbyte SDRAM, configured as 64M words x 16, provided by two EtronTech EM63B165TS-5SG chips). There will also be access to 10ns 2Mbyte SRAM, provided by a Cypress CY7C1061G(E)30 1M words x 16 - this could be doubled if needed to 4Mbytes by using two chips and the inverted select line).

Stereo audio from the Jazz chip comes in though a PCM1808 audio chip, this takes the headphone output from the Jazz chip and samples it at up to 24-bit 96khz (I2S) for digital output through the HDMI connector.

Various FPGA “emulators” use this FPGA to recreate the Amiga, Atari STE, SNES, NES, C64, Vic 20, PacMan, Spectrum, and MSX2 Yamaha VDP.

Prototype Next (KS1) Next (KS2)
Device GW5A XC6LX9 XC7A15T
LUT4 23,040 9,152 16,640
Flip-Flop (FF) / Register 23,040 11,440
Shadow SRAM SSRAM (Kbits) 180 90 200
Block SRAM BSRAM (Kbits) 1008 576 900
Number of BSRAM 56 50
PSRAM (Mbits)
18x18 Multipliers 16
DSP 28 45
PLLs 6 2 5
I/O banks 8 4 5
Max GPIOs 239 200 250
Core voltage (V) 1.0 0.9-1.0 0.9-1.0

The FPGA can load both 128-bit AES encrypted and unencrypted images. They key is held in a locked secure location in the FPGA, once locked it cannot be read or written. This will allow encrypted images whilst allowing others to load unencrypted images. Our 128-bit AES key will remain confidential. We will set the key before distribution or else someone else could set the key and lock it.

The DeMon chip will program the FPGA using the JTAG interface. As the DeMon will have it’s own flash memory, it can program it with an image from that at boot – eg to display a logo or an effect whilst the rest of the system boots.

JTAG lines

  • TCK out this is connected to all devices
  • TMS out this is connected to all devices
  • TDI out the TDO line from a device goes to the TDI input of the device
  • TDO in the last device TDO is connected to this

  • Ready
  • Config
  • Done

    • On the Tang Primer 25k, the debug test points are the JTAG lines.

    FRAM interfaces

    The main "chips" (Duo, DeMon, SticKey and Jazz) will eventually interface to Jazz (an FPGA) using something called a FRAM interface. This is basically a "Fake QSPI RAM" interface, the host chips map this into their memory map. All chips will have mapped shared access to Razz's 4MB SRAM, leaving 12MB (each) spare memory map in the FRAM16 interfaces, and 124MB spare in the Duo's FRAM256 interface (128MB of space is mapped to the 128MB SDRAM in the Razz).

    Prototype 1: Using Tang Primer 25K

    Prototype 1 has HDMI out, 64MB 5ns SDRAM, 8MB QSPI NOR Flash, Duo FRAM256 interface, I2S raw audio sample from Jazz, VSync out, HSync out, Pixel clock out, Jazz SPI master, I2C system master (all chips).

    J3

    RAM Function Pin Pin Function RAM
    D0 K2 IOR20B 1 2 K1 IOR20A D1
    D2 L1 IOR18B 3 4 L2 IOR18A D3
    D4 K4 IOR22B 5 6 J4 IOR22A D5
    D6 G1 IOR24B 7 8 G2 IOR24A D7
    D15L3 IOR31B 9 10 L4 IOR31A D14
    +V 5V 11 12 GND GND
    D13C2 IOB04B 13 14 B2 IOB4A D12
    D11F1 IOB26B 15 16 F2 IOB26A D10
    D9 A1 IOB24A 17 18 E1 IOB12B D8
    A12D1 IOB14B 19 20 E3 IOB60A CLK
    A9 J2 IOR33B 21 22 J1 IOB33A A11
    A7 H4 IOB89B 23 24 G4 IOB89A A8
    A5 H2 IOB91B 25 26 H1 IOB91A A6
    WE J7 IOT21B 27 28 K7 IOT21A A4
    LDML8 IOT19B 29 30 L7 IOT19A UDM
    CASK10 IOT15B 31 32 L10 IOT15A RAS
    CS0K9 IOT31B 33 34 L9 IOT31A BA0
    BA1K8 IOT56B 35 36 J8 IOT56A A10
    A0 F6 IOT58B 37 38 F7 IOT58a A1
    A2 J10 IOT1B 39 40 J11 IOT1A A3

    J4

    Pin FPGA Description Pin FPGA Description
    2 3v3 1 3v3
    4 GND 3 GND
    6 C10 IOL5B Duo memory WP 5 C11 IOL5A Duo memory HOLD
    8 B10 IOL12B Duo memory MOSI 7 B11 IOL12A Duo memory MISO
    10 D10 IOL9B Duo memory SCK 9 D11 IOL9A Duo memory CS
    12 G10 IOT7B I2S PCM1808 BCK 11 G11 IOT7A I2S PCM1808 DATA

    J5

    Pin FPGA Description Pin FPGA Description
    2 3v3 1 3v3
    4 GND 3 GND
    6 K5 IOT63B I2S PCM1808 LRCK 5 L5 IOT63A Pixel clock out
    8 L11 IOT11B SPI master MISO 7 K11 IOT11A SPI master MOSI
    10 E10 IOL3B SPI master SCK 9 E11 IOL3A SPI master CS0 Jazz
    12 A10 IOL14B I2C master SCL 11 A11 IOL14A I2C master SDA

    J6

    Pin FPGA Description Pin FPGA Description
    2 3v3 1 3v3
    4 GND 3 GND
    6 J5 IOT61B HDMI CKN CTRL/STATUS 5 H5 IOT61A HDMI CKP CTRL/STATUS
    8 H7 IOT66B HDMI D0N BLUE, H/V SYNC7 H8 IOT66A HDMI D0P BLUE, H/V SYNC
    10 G8 IOT68B HDMI D1N GREEN, CTL 0/19 G7 IOT68A HDMI D1P GREEN, CTL 0/1
    12 G5 IOT72B HDMI D2N RED, CTL 2/3 11 F5 IOT72A HDMI D2P RED, CTL 2/3/td>

    USB A host

    Pin FPGA Description
    1 L6 IOT23A USB-A P - VSync out
    2 K6 IOT23B USB-A N - HSync out
    3 E8 READY USB DP Pull

    Debug

    Pin FPGA Description
    1 B1 JTAG TMS JTAG TMS
    2 A3 JTAG TDI JTAG TDI
    3 C1 JTAG TCK JTAG TCK – with 5.1k resistor to GND
    4 5v
    5 A2 JTAG TDO JTAG TDO
    6 GND
    7 3v3
    8 BL616 Enable, connect to GND to disable BL616
    B3 IOB56A FPGA UART TX UART TX – to BL616 UART RX
    C3 IOB56B FPGA UART RX UART RX – to BL616 UART TX

    LED

    Pin FPGA Description
    3 E8 READY Ready = 1, not ready = 0
    4 D7 DONE Done = 1, fail = 0

    Button

    Pin FPGA Description
    1 H11 IOT3A S1
    2 H10 IOT3B S2

    4 pin connector

    Pin FPGA Description
    1 D8 Reconfig
    2 GND
    3 E8 Ready
    4 D7 Done

    Prototype 2: Using core board (Gowin GW5A-LV25MG121NES)

    Prototype 2 has HDMI out, 128MB 5ns SDRAM, 8MB QSPI NOR Flash, Duo FRAM256 interface, SticKey FRAM16 interface, Jazz FRAM16 interface, I2S raw audio sample from Jazz, VSync out, HSync out, Pixel clock out, Jazz SPI master, I2C system master (all chips).

    J1

    Description FPGA Pin Pin FPGA Description
    GND 2 1 GND
    J6_5 Jazz memory CS H5 IOT61A 4 3 L9 IOT31A J3_34 SDRAM BA0
    J6_6 Jazz memory SCK J5 IOT61B 6 5 K9 IOT31B J3_33 SDRAM CS0
    J5_5 Jazz memory HOLD L5 IOT63A 8 7 J8 IOT56A J3_36 SDRAM A10
    J5_6 Jazz memory WP K5 IOT63B 10 9 K8 IOT56B J3_35 SDRAM BA1
    J6_7 Jazz memory MISO H8 IOT66A 12 11 F7 IOT58A J3_38 SDRAM A1
    J6_8 Jazz memory MOSI H7 IOT66B 14 13 F6 IOT58B J3_37 SDRAM A0
    J6_9 I2S PCM1808 BCK G7 IOT68A 16 15 GND
    J6_10 I2S PCM1808 DAT G8 IOT68B 18 17 E8 READY FPGA Ready (LED 3)
    J6_11 I2C master F5 IOT72A 20 19 B3 IOB56A I2S PCM1808 LRCK
    J6_12 I2C master G5 IOT72B 22 21 C3 IOB56B Pixel clock out
    VCC IO 0 24 23 E3 IOB60A J3_20 SDRAM CLK
    VCC IO 1 26 25 D7 DONE FPGA Done (LED 4)
    GND 28 27 GND
    USB P - VSync out L6 IOT23A 30 29 VCC IO 6
    USB N - HSync out K6 IOT23B 32 31 VCC IO 7
    J3_28 SDRAM A4 K7 IOT21A 34 33 J11 IOT1A J3_40 SDRAM A3
    J3_27 SDRAM WE J7 IOT21B 36 35 J10 IOT1B J3_39 SDRAM A2
    J3_30 SDRAM UDM L7 IOT19A 38 37 H11 IOT3A S1 - SPI master MISO
    J3_29 SDRAM LDM L8 IOT19B 40 39 H10 IOT3B S2 - SPI master MOSI
    J3_32 SDRAM RAS L10 IOT15A 42 41 G11 IOT7A J4_11 SPI master SCK
    J3_31 SDRAM CAS K10 IOT15B 44 43 G10 IOT7B J4_12 SPI master CS0 Jazz
    J5_7 DeMon memory CS K11 IOT11A 46 45 GND
    J5_8 DeMon memory SCK L11 IOT11B 48 47 D11 IOL9A J4_9 Duo memory CS
    GND 50 49 D10 IOL9B J4_10 Duo memory SCK
    J5_9 DeMon memory HOLD E11 IOL3A 52 51 C11 IOL5A J4_5 Duo memory HOLD
    J5_10 DeMon memory WP E10 IOL3B 54 53 C10 IOL5B J4_6 Duo memory WP
    J5_11 DeMon memory MISO A11 IOL14A 56 55 B11 IOL12A J4_7 Duo memory MISO
    J5_12 DeMon memory MOSI A10 IOL14B 58 57 B10 IOL12B J4_8 Duo memory MOSI
    GND 60 59 GND

    J2

    Description FPGA Pin Pin FPGA Description
    VCC IO 2 2 1 GND
    VCC IO 3 4 3 B2 IOB4A J3_14 SDRAM D12
    J3_4 SDRAM D3 L2 IOR18A 6 5 C2 IOB4B J3_13 SDRAM D13
    J3_3 SDRAM D2 L1 IOR18B 8 7 F2 IOB26A J3_16 SDRAM D10
    J3_2 SDRAM D1 K1 IOR20A 10 9 F1 IOB26B J3_15 SDRAM D11
    J3_1 SDRAM D0 K2 IOR20B 12 11 A1 IOB24A J3_17 SDRAM D9
    J3_6 SDRAM D5 J4 IOR22A 14 13 D8 RECONFIGFPGA Reconfig
    J3_5 SDRAM D4 K4 IOR22B 16 15 E1 IOB12B J3_18 SDRAM D8
    J3_8 SDRAM D7 G2 IOR24A 18 17 D1 IOB14B J3_19 SDRAM A12
    J3_7 SDRAM D6 G1 IOR24B 20 19 GND
    J3_10 SDRAM D14L4 IOR31A 22 21 C1 JTAG TCKJTAG TCK– with 5.1k res to GND
    J3_9 SDRAM D15 L3 IOR31B 24 23 B1 JTAG TMSJTAG TMS
    J3_22 SDRAM A11J1 IOR33A 26 25 A2 JTAG TDOJTAG TDO
    J3_21 SDRAM A9 J2 IOR33B 28 27 A3 JTAG TDIJTAG TDI
    J3_24 SDRAM A8 G4 IOB89A 30 29 GND
    J3_23 SDRAM A7 H4 IOB89B 32 31 M0 D3P
    J3_26 SDRAM A6 H1 IOB91A 34 33 M0 D3N
    J3_25 SDRAM A5 H2 IOB91B 36 35 GND
    VDD 1v8 38 37 M0 D2P HDMI D2P RED, CTL2/3
    VDD 1v8 40 39 M0 D2N HDMI D2N RED, CTL2/3
    VDD 2v5 42 41 GND
    VDD 2v5 44 43 M0 CKP HDMI CKP CTRL/STATUS
    VDD 3v3 46 45 M0 CKN HDMI CKN CTRL/STATUS
    VDD 3v3 48 47 GND
    VDD 3v3 50 49 M0 D1P HDMI D1P GREEN, CTL0/1
    VDD 5v 52 51 M0 D1N HDMI D1N GREEN, CTL0/1
    VDD 5v 54 53 GND
    VDD 5v 56 55 M0 D0P HDMI D0P BLUE, H/V SYNC
    VDD 5v 58 57 M0 D0N HDMI D0N BLUE, H/V SYNC
    VDD 5v 60 59 GND

    Prototype 3: Using a GW5A-LV25UG324SC2

    Prototype 3 has HDMI out, VGA 24-bit (888) RGB out, 128MB 5ns SDRAM, 4MB 10ns SRAM, 8MB PSRAM, 16MB QSPI NOR Flash, Duo FRAM256 interface, DeMon FRAM16 interface, SticKey FRAM16 interface, Jazz FRAM16 interface, I2S raw audio sample from Jazz, VSync out, HSync out, Pixel clock out, Jazz SPI master, Duo SPI slave, I2C system master (all chips), UART TX to DeMon, “Next” accelerator port, 34 GPIO pins for use with the "Interface port" (also on this port are d0-d15, a0/1-a20/21 (16/8 bit word), udm/ldm, WE, OE, L/R audio mix in, mono mix audio out, various debug pins, etc)..

    Pin Default Description
    IOB01ARECONFIGN Reconfig FPGA
    IOB02A Interface GPIO 0
    IOB02B Interface GPIO 1
    IOB04ALPLL1_T_FB0 Interface GPIO 2
    IOB04BLPLL1_C_FB0 Interface GPIO 3
    IOB06A Interface GPIO 4
    IOB06B Interface GPIO 5
    IOB08ASO Duo SPI slave MISO
    IOB08B Interface GPIO 6
    IOB10ASSPI_CN Duo SPI slave CSn
    IOB10BSI Duo SPI slave MOSI
    IOB12AGCLKT_10B/LPLL1_T_IN1 Interface GPIO 7
    IOB12BGCLKC_10B/LPLL1_C_IN1 Interface GPIO 8
    IOB14ASSPI_CLK Duo SPI slave CLK
    IOB14BCLKHOLD_N Interface GPIO 9
    IOB16A Interface GPIO 10
    IOB16B Interface GPIO 11
    IOB18A Interface GPIO 12
    IOB18B Interface GPIO 13
    IOB20A Interface GPIO 14
    IOB20B Interface GPIO 15
    IOB22A Interface GPIO 16
    IOB22B Interface GPIO 17
    IOB24A Interface GPIO 18
    IOB24B Interface GPIO 19
    IOB26AGCLKT_12 Interface GPIO 20
    IOB26BGCLKC_12 Interface GPIO 21
    IOB29AGCLKT_11A Interface GPIO 22
    IOB29BGCLKC_11A Interface GPIO 23
    IOB31AGCLKT_10A/BPLL_T_FB0 Interface GPIO 24
    IOB31BGCLKC_10A/BPLL_C_FB0 Interface GPIO 25
    IOB33AGCLKT_9A/BPLL_T_IN1 Interface GPIO 26
    IOB33BGCLKC_9A/EMCCLK/BPLL_C_IN1 EMCCLK
    IOB35AGCLKT_8 Interface A24
    IOB35BGCLKC_8 Interface A23
    IOB37AREADY READY FPGA READY, LED out
    IOB37BMCS_N/CSO_B Flash SPI CS
    IOB39A Interface A22
    IOB39B Interface A21
    IOB41A Interface select A
    IOB41B Interface select B
    IOB43A Interface RESET output
    IOB43B Interface Connected input
    IOB45A Jazz HS0a
    IOB45B Jazz HS0b
    IOB48A Jazz HS1a
    IOB48B Jazz HS1b
    IOB50A Duo HSa
    IOB50B Duo HSb
    IOB52AMODE1 Set to 0 via resistor
    IOB52B UART TX (to DeMon)
    IOB54AMI2 Flash SPI WP
    IOB54BMI3 Flash SPI HOLD
    IOB56A I2C Master SCL
    IOB56B I2C Master SDA
    IOB58AMISO Flash SPI MISO
    IOB58BMOSI Flash SPI MOSI
    IOB60A PS-RAM CS0
    IOB60B Jazz CSn
    IOB62ACCLK Flash SPI CLK
    IOB62BMODE0 Set to 1 via resistor
    IOB64ADONE FPGA DONE, LED out
    IOB65A RGB R0
    IOB65BDOUT RGB R1
    IOB67A RGB R2
    IOB67B RGB R3
    IOB69A RGB R4
    IOB69B RGB R5
    IOB71A RGB R6
    IOB71B RGB R7
    IOB73A RGB G0
    IOB73B RGB G1
    IOB75AGCLKT_6B RGB G2
    IOB75BVGCLKC_6B RGB G3
    IOB77A RGB G4
    IOB77B RGB G5
    IOB79A RGB G6
    IOB79B RGB G7
    IOB81A RGB B0
    IOB81B RGB B1
    IOB83A RGB B2
    IOB83B RGB B3
    IOB85A RGB B4
    IOB85B RGB B5
    IOB87A RGB B6
    IOB87B RGB B7
    IOB89AGCLKT_7/BPLL_T_IN0 Chromakey
    IOB89BGCLKC_7/BPLL_C_IN0 VSync out
    IOB91AGCLKT_6A HSync out
    IOB91BGCLKC_6A Pixel clock out
    IOL03AGCLKT_14/LPLL0_T_IN2/LPLL0_T_FB0ACC GPIO 0
    IOL03BGCLKC_14/LPLL0_C_IN2/LPLL0_C_FB0ACC GPIO 1
    IOL05AGCLKT_13/LPLL0_T_IN1/LPLL0_T_FB1ACC GPIO 2
    IOL05BGCLKC_13/LPLL0_C_IN1/LPLL0_C_FB1ACC GPIO 3
    IOL07A ACC GPIO 4
    IOL07B ACC GPIO 5
    IOL09A ACC GPIO 6
    IOL09B ACC GPIO 7
    IOL12A ACC GPIO 8
    IOL12B ACC GPIO 9
    IOL14ALPLL1_T_IN0 ACC GPIO 10
    IOL14BLPLL1_C_IN0 ACC GPIO 11
    IOL16A ACC GPIO 12
    IOL16B ACC GPIO 13
    IOL18A ACC GPIO 14
    IOL18B ACC GPIO 15
    IOL21A ACC GPIO 16
    IOL21B ACC GPIO 17
    IOL23A ACC GPIO 18
    IOL23B ACC GPIO 19
    IOL25A ACC GPIO 20
    IOL25B ACC GPIO 21
    IOL27A ACC GPIO 22
    IOL27B ACC GPIO 23
    IOL29A ACC GPIO 24
    IOL29B ACC GPIO 25
    IOL31A ACC GPIO 26
    IOL31B ACC GPIO 27
    IOR01ATCK JTAG TCK
    IOR01BTDI JTAG TDI
    IOR03ATMS JTAG TMS
    IOR03BTDO JTAG TDO
    IOR05A FRAM0 - Duo memory CS
    IOR05B FRAM0 - Duo memory SCK
    IOR07A FRAM0 - Duo memory HOLD
    IOR07B FRAM0 - Duo memory WP
    IOR09A FRAM0 - Duo memory MISO
    IOR09B FRAM0 - Duo memory MOSI
    IOR12A FRAM1 – DeMon memory CS
    IOR12B FRAM1 – DeMon memory SCK
    IOR14A FRAM1 – DeMon memory HOLD
    IOR14B FRAM1 – DeMon memory WP
    IOR16A FRAM1 – DeMon memory MISO
    IOR16B FRAM1 – DeMon memory MOSI
    IOR18A FRAM2 – Jazz memory CS
    IOR18B FRAM2 – Jazz memory SCK
    IOR20A FRAM2 – Jazz memory HOLD
    IOR20B FRAM2 – Jazz memory WP
    IOR22A FRAM2 – Jazz memory MISO
    IOR22B FRAM2 – Jazz memory MOSI
    IOR24A FRAM3 - ESP32-C5 memory CS
    IOR24B FRAM3 - ESP32-C5 memory SCK
    IOR26A FRAM3 - ESP32-C5 memory HOLD
    IOR26B FRAM3 - ESP32-C5 memory WP
    IOR29A FRAM3 - ESP32-C5 memory MISO
    IOR29B FRAM3 - ESP32-C5 memory MOSI
    IOR31AGCLKT_4/RPLL1_T_IN0/RPLL1_T_FB1 I2S PCM1808 SCKI
    IOR31BGCLKC_4/RPLL1_C_IN0/RPLL1_C_FB1 I2S PCM1808 LRCK
    IOR33AGCLKT_5/RPLL1_T_IN1/RPLL1_T_FB0 I2S PCM1808 BCK
    IOR33BGCLKC_5/RPLL1_C_IN1/RPLL1_C_FB0 I2S PCM1808 DAT
    IOR35A HDMI D0N BLUE, H/V SYNC
    IOT01AGCLKT_15/LPLL0_T_IN0 HDMI D0P BLUE, H/V SYNC
    IOT01BGCLKC_15/LPLL0_C_IN0 HDMI D1N GREEN, CTL0/1
    IOT03AGCLKT_16 HDMI D1P GREEN, CTL0/1
    IOT03BGCLKC_16 HDMI D2N RED, CTL2/3
    IOT05A HDMI D2P RED, CTL2/3
    IOT05B HDMI CKN CTRL/STATUS
    IOT07A HDMI CKP CTRL/STATUS
    IOT07B SDRAM20 CLK (rearrange below for clock)
    IOT09A SDRAM33 CS0
    IOT09B SDRAM32 RAS
    IOT11A SDRAM31 CAS
    IOT11B SDRAM27 WE
    IOT13A SDRAM UDM
    IOT13B SDRAM LDM
    IOT15A SDRAM37 A0
    IOT15B SDRAM38 A1
    IOT17A SDRAM39 A2
    IOT17B SDRAM40 A3
    IOT19A SDRAM28 A4
    IOT19B SDRAM25 A5
    IOT21A SDRAM26 A6
    IOT21B SDRAM23 A7
    IOT23A SDRAM24 A8
    IOT23B SDRAM21 A9
    IOT25A SDRAM36 A10/AP
    IOT25B SDRAM22 A11
    IOT27A SDRAM19 A12
    IOT27B SDRAM34 BA0
    IOT29APUDC_B Pull Up DC_B / Reserved SRAM CE (tied to low via 1K resistors)
    IOT29B SDRAM35 BA1
    IOT31A SDRAM01 D0
    IOT31B SDRAM02 D1
    IOT33A SDRAM03 D2
    IOT33B SDRAM04 D3
    IOT35A SDRAM05 D4
    IOT35B SDRAM06 D5
    IOT37A SDRAM07 D6
    IOT37B SDRAM08 D7
    IOT39A SDRAM18 D8
    IOT39B SDRAM17 D9
    IOT41A SDRAM16 D10
    IOT41B SDRAM15 D11
    IOT43A SDRAM14 D12
    IOT43B SDRAM13 D13
    IOT45A SDRAM10 D14
    IOT45B SDRAM09 D15
    IOT48A SRAM OE
    IOT48B SRAM CE
    IOT50A SRAM WE
    IOT50B SRAM UDM
    IOT52A SRAM LDM
    IOT52B SRAM A0
    IOT54A SRAM A1
    IOT54B SRAM A2
    IOT56AGCLKT_0/TPLL_T_IN1/TPLL_T_FB1 SRAM A3
    IOT56BGCLKC_0/TPLL_C_IN1/TPLL_C_FB1 SRAM A4
    IOT58AGCLKT_1/TPLL_T_IN2/TPLL_T_FB0 SRAM A5
    IOT58BGCLKC_1/TPLL_C_IN2/TPLL_C_FB0 SRAM A6
    IOT61AGCLKT_2/TPLL_T_IN0 SRAM A7
    IOT61BGCLKC_2/TPLL_C_IN0 SRAM A8
    IOT63AGCLKT_3/RPLL0_T_IN0 SRAM A9
    IOT63BGCLKC_3/RPLL0_C_IN0 SRAM A10
    IOT66A SRAM A11
    IOT66B SRAM A12
    IOT68A SRAM A13
    IOT68B SRAM A14
    IOT70A SRAM A15
    IOT70B SRAM A16
    IOT72A SRAM A17
    IOT72B SRAM A18
    IOT74A SRAM A19
    IOT74B SRAM A20
    IOT76A SRAM D0
    IOT76B SRAM D1
    IOT78A SRAM D2
    IOT78B SRAM D3
    IOT80A SRAM D4
    IOT80B SRAM D5
    IOT83A SRAM D6
    IOT83B SRAM D7
    IOT85A SRAM D8
    IOT85B SRAM D9
    IOT87A SRAM D10
    IOT87B SRAM D11
    IOT89ARPLL0_T_FB1 SRAM D12
    IOT89BRPLL0_C_FB1 SRAM D13
    IOT91ARPLL0_T_IN1/RPLL0_T_FB0 SRAM D14
    IOT91BRPLL0_C_IN1/RPLL0_C_FB0 SRAM D15

    Special pins

    Pin Default Description
    IOB01ARECONFIG_N Global reset GowinCONFIG logic signal, active low
    IOB33BGC9A/BCIN1/ EMCCLK As a configuration pin, it is an input pin. Used to configure the optional external clock input in a master mode (versus the internal configuration oscillator). For master modes: FPGA can optionally switch to EMCCLK as the clock source. For JTAG and slave modes: EMCCLK is ignored and can be left unconnected.
    IOB37AREADY High, the device can be programmed and configured currently; Low, the device cannot be programmed and configured currently
    IOB37BMCS_N/CSO_B MSPI Mode: Enable signal MCS_N, active-low
    IOB52AMODE1 Set to 0 via resistor As a Master, FPGA reads data from external Flash (or other devices) via the SPI interface for configuration
    IOB54AMI2 MSPI Mode: In X4 mode, the input pin of parallel data bit 2 that connects to pin DQ2/W#/WP#/IO2 of external Flash device respectively
    IOB54BMI3 MSPI Mode: In X4 mode, the input pin of parallel data bit 3 that connects to pin DQ3/HOLD#/IO3 of external Flash device respectively
    IOB58AMISO MSPI Mode: Serial data input in X1 mode; In X2 and X4 modes, the input pin of parallel data bit 1 that connects to DQ1/Q/SO/IO1 pins of external Flash device
    IOB58BMOSI MSPI Mode: Serial instruction and address output, in X2 and X4 modes, the input pin of parallel data bit 0 that connects to DQ0/D/SI/IO0 pins of external Flash device
    IOB62ACCLK Configuration Clock Slave Mode: CCLK is input and need connect to external clock source Master Mode: CCLK is output
    IOB62BMODE0 Set to 1 via resistor As a Master, FPGA reads data from external Flash (or other devices) via the SPI interface for configuration
    IOB64ADONE Input: When the DONE signal is low, delay the chip to activate. Activate the chip until the DONE signal is high. Output: High, the programming configuration has been completed successfully; Low, the programming configuration has not been completed or failed.
    IOR01ATCK JTAG Mode: Serial clock input
    IOR01BTDI JTAG Mode: Serial data input
    IOR03ATMS JTAG Mode: Serial mode input
    IOR03BTDO JTAG Mode: Serial data output
    IOT29APUDC_B Active-low, weak pull-up selection signal pin during configuration： Enable internal weak pull-up resistor during configuration after FPGA power up PUDC_B low: all GPIOs except PUDC_B weak pull-up PUDC_B high: all GPIOs are in high impedance PUDC_B are not allowed to be left floating during configuration

    Links

  • youtube.com/watch?v=2aCpYgerxq8
  • youtube.com/watch?v=wd3p9nQLfUY
  • youtube.com/watch?v=p30GwtfA5vk
  • Tutorial - learn.lushaylabs.com/tang-nano-series/

    • Important: The Ant32 and Ant64 are both still at early design and prototype stage, everything you see here is subject to change.