“Razz” – Raster Engine

This reads a special “display” program to generate the screen layout, from that it will also generate the video signal that is output via HDMI.

The FPGA is a GoWin GW5A-LV60UG324SC1/I0.

The Razz chip will have direct access to its own 1.25ns 512MByte DDR3 SDRAM, configured as 512M words x 16. This is provided by a MT41J256M16 chip. There will also be access to 10ns 4Mbyte SRAM, provided by a IS61WV204816BLL 2M words x 16.

Stereo audio from the Jazz chip comes in though a PCM1808 audio chip, this takes the headphone output from the Jazz chip and samples it at up to 24-bit 96khz (I2S) for digital output through the HDMI connector.

Various FPGA “emulators” use this FPGA to recreate the Amiga, Atari STE, SNES, NES, C64, Vic 20, PacMan, Spectrum, and MSX2 Yamaha VDP.

Prototype Final Next (KS1) Next (KS2)
Device GW5A-25 GW5A-60 XC6LX9 XC7A15T
LUT4 23,040 59,904 9,152 16,640
Flip-Flop (FF) / Register 23,040 59,904 11,440
Shadow SRAM SSRAM (Kbits) 180 468 90 200
Block SRAM BSRAM (Kbits) 1008 2124 576 900
Number of BSRAM 56 118 50
18x18 Multipliers 16
DSP 28 118 45
PLLs 6 8 2 5
I/O banks 8 11 4 5
Max GPIOs 80 (36 LVDS) 222 (106 LVDS) 200 250
Core voltage (V) 0.9-1.2 0.9-1.2 0.9-1.0 0.9-1.0

The FPGA can load both 128-bit AES encrypted and unencrypted images. They key is held in a locked secure location in the FPGA, once locked it cannot be read or written. This will allow encrypted images whilst allowing others to load unencrypted images. Our 128-bit AES key will remain confidential. We will set the key before distribution or else someone else could set the key and lock it.

The DeMon chip will program the FPGA using the JTAG interface. As the DeMon will have it’s own flash memory, it can program it with an image from that at boot – eg to display a logo or an effect whilst the rest of the system boots.

JTAG lines

  • TCK out this is connected to all devices
  • TMS out this is connected to all devices
  • TDI out the TDO line from a device goes to the TDI input of the device
  • TDO in the last device TDO is connected to this

  • Ready
  • Config
  • Done

    • On the Tang Primer 25k, the debug test points are the JTAG lines.

    FRAM interfaces

    The main "chips" (SG2002, DeMon, SticKey and Jazz) will eventually interface to Jazz (an FPGA) using something called a FRAM interface. This is basically a "Fake QSPI RAM" interface, the host chips map this into their memory map. All chips will have mapped shared access to Razz's 4MB SRAM, leaving 12MB (each) spare memory map in the FRAM16 interfaces, and 124MB spare in the SG2002's FRAM256 interface (128MB of space is mapped to the 128MB SDRAM in the Razz).

    Prototype 1: Using Tang Primer 25K

    Prototype 1 has HDMI out, 64MB 5ns SDRAM, 8MB QSPI NOR Flash, SG2002 FRAM256 interface, I2S raw audio sample from Jazz, VSync out, HSync out, Pixel clock out, Jazz SPI master, I2C system master (all chips).

    J3

    RAM Function Pin Pin Function RAM
    D0 K2 IOR20B 1 2 K1 IOR20A D1
    D2 L1 IOR18B 3 4 L2 IOR18A D3
    D4 K4 IOR22B 5 6 J4 IOR22A D5
    D6 G1 IOR24B 7 8 G2 IOR24A D7
    D15L3 IOR31B 9 10 L4 IOR31A D14
    +V 5V 11 12 GND GND
    D13C2 IOB04B 13 14 B2 IOB4A D12
    D11F1 IOB26B 15 16 F2 IOB26A D10
    D9 A1 IOB24A 17 18 E1 IOB12B D8
    A12D1 IOB14B 19 20 E3 IOB60A CLK
    A9 J2 IOR33B 21 22 J1 IOB33A A11
    A7 H4 IOB89B 23 24 G4 IOB89A A8
    A5 H2 IOB91B 25 26 H1 IOB91A A6
    WE J7 IOT21B 27 28 K7 IOT21A A4
    LDML8 IOT19B 29 30 L7 IOT19A UDM
    CASK10 IOT15B 31 32 L10 IOT15A RAS
    CS0K9 IOT31B 33 34 L9 IOT31A BA0
    BA1K8 IOT56B 35 36 J8 IOT56A A10
    A0 F6 IOT58B 37 38 F7 IOT58a A1
    A2 J10 IOT1B 39 40 J11 IOT1A A3

    J4

    Pin FPGA Description Pin FPGA Description
    2 3v3 1 3v3
    4 GND 3 GND
    6 C10 IOL5B SG2002 memory WP 5 C11 IOL5A SG2002 memory HOLD
    8 B10 IOL12B SG2002 memory MOSI 7 B11 IOL12A SG2002 memory MISO
    10 D10 IOL9B SG2002 memory SCK 9 D11 IOL9A SG2002 memory CS
    12 G10 IOT7B I2S PCM1808 BCK 11 G11 IOT7A I2S PCM1808 DATA

    J5

    Pin FPGA Description Pin FPGA Description
    2 3v3 1 3v3
    4 GND 3 GND
    6 K5 IOT63B I2S PCM1808 LRCK 5 L5 IOT63A Pixel clock out
    8 L11 IOT11B SPI master MISO 7 K11 IOT11A SPI master MOSI
    10 E10 IOL3B SPI master SCK 9 E11 IOL3A SPI master CS0 Jazz
    12 A10 IOL14B I2C master SCL 11 A11 IOL14A I2C master SDA

    J6

    Pin FPGA Description Pin FPGA Description
    2 3v3 1 3v3
    4 GND 3 GND
    6 J5 IOT61B HDMI CKN CTRL/STATUS 5 H5 IOT61A HDMI CKP CTRL/STATUS
    8 H7 IOT66B HDMI D0N BLUE, H/V SYNC7 H8 IOT66A HDMI D0P BLUE, H/V SYNC
    10 G8 IOT68B HDMI D1N GREEN, CTL 0/19 G7 IOT68A HDMI D1P GREEN, CTL 0/1
    12 G5 IOT72B HDMI D2N RED, CTL 2/3 11 F5 IOT72A HDMI D2P RED, CTL 2/3/td>

    USB A host

    Pin FPGA Description
    1 L6 IOT23A USB-A P - VSync out
    2 K6 IOT23B USB-A N - HSync out
    3 E8 READY USB DP Pull

    Debug

    Pin FPGA Description
    1 B1 JTAG TMS JTAG TMS
    2 A3 JTAG TDI JTAG TDI
    3 C1 JTAG TCK JTAG TCK – with 5.1k resistor to GND
    4 5v
    5 A2 JTAG TDO JTAG TDO
    6 GND
    7 3v3
    8 BL616 Enable, connect to GND to disable BL616
    B3 IOB56A FPGA UART TX UART TX – to BL616 UART RX
    C3 IOB56B FPGA UART RX UART RX – to BL616 UART TX

    LED

    Pin FPGA Description
    3 E8 READY Ready = 1, not ready = 0
    4 D7 DONE Done = 1, fail = 0

    Button

    Pin FPGA Description
    1 H11 IOT3A S1
    2 H10 IOT3B S2

    4 pin connector

    Pin FPGA Description
    1 D8 Reconfig
    2 GND
    3 E8 Ready
    4 D7 Done

    Special pins

    Pin Default Description
    IOB01ARECONFIG_N Global reset GowinCONFIG logic signal, active low
    IOB33BGC9A/BCIN1/ EMCCLK As a configuration pin, it is an input pin. Used to configure the optional external clock input in a master mode (versus the internal configuration oscillator). For master modes: FPGA can optionally switch to EMCCLK as the clock source. For JTAG and slave modes: EMCCLK is ignored and can be left unconnected.
    IOB37AREADY High, the device can be programmed and configured currently; Low, the device cannot be programmed and configured currently
    IOB37BMCS_N/CSO_B MSPI Mode: Enable signal MCS_N, active-low
    IOB52AMODE1 Set to 0 via resistor As a Master, FPGA reads data from external Flash (or other devices) via the SPI interface for configuration
    IOB54AMI2 MSPI Mode: In X4 mode, the input pin of parallel data bit 2 that connects to pin DQ2/W#/WP#/IO2 of external Flash device respectively
    IOB54BMI3 MSPI Mode: In X4 mode, the input pin of parallel data bit 3 that connects to pin DQ3/HOLD#/IO3 of external Flash device respectively
    IOB58AMISO MSPI Mode: Serial data input in X1 mode; In X2 and X4 modes, the input pin of parallel data bit 1 that connects to DQ1/Q/SO/IO1 pins of external Flash device
    IOB58BMOSI MSPI Mode: Serial instruction and address output, in X2 and X4 modes, the input pin of parallel data bit 0 that connects to DQ0/D/SI/IO0 pins of external Flash device
    IOB62ACCLK Configuration Clock Slave Mode: CCLK is input and need connect to external clock source Master Mode: CCLK is output
    IOB62BMODE0 Set to 1 via resistor As a Master, FPGA reads data from external Flash (or other devices) via the SPI interface for configuration
    IOB64ADONE Input: When the DONE signal is low, delay the chip to activate. Activate the chip until the DONE signal is high. Output: High, the programming configuration has been completed successfully; Low, the programming configuration has not been completed or failed.
    IOR01ATCK JTAG Mode: Serial clock input
    IOR01BTDI JTAG Mode: Serial data input
    IOR03ATMS JTAG Mode: Serial mode input
    IOR03BTDO JTAG Mode: Serial data output
    IOT29APUDC_B Active-low, weak pull-up selection signal pin during configuration： Enable internal weak pull-up resistor during configuration after FPGA power up PUDC_B low: all GPIOs except PUDC_B weak pull-up PUDC_B high: all GPIOs are in high impedance PUDC_B are not allowed to be left floating during configuration

    Links

  • youtube.com/watch?v=2aCpYgerxq8
  • youtube.com/watch?v=wd3p9nQLfUY
  • youtube.com/watch?v=p30GwtfA5vk
  • Tutorial - learn.lushaylabs.com/tang-nano-series/

    • Important: The Ant32 and Ant64 are both still at early design and prototype stage, everything you see here is subject to change.