RGB Video Output

A compact, fully-independent secondary video + audio output based on standard DE-15 VGA plus a 3.5 mm stereo audio jack. Drives VGA monitors and multisync CRTs directly, and reaches SCART TVs / S-video sets / component-input displays through off-the-shelf external adapters.

The port carries everything on a single HDMI stream from the host FPGA's secondary HDMI TX. An AG6201 bridge chip on the PCB extracts both video (as analog RGB + separate H/V sync on standard VGA pins) and audio (via its embedded stereo audio DAC, decoded from the HDMI audio-island packets, output on the 3.5 mm jack). Video and audio are fully independent of the host's main HDMI output and main audio codec.

Design goals

• Standard connectors only. A DE-15 VGA socket and a 3.5 mm TRS audio jack — both placed adjacent on the back panel. Any VGA cable and any 3.5 mm audio cable the user already owns works. No custom pinouts, no machine-specific cables.
• DDC / EDID connected. The AG6201's VGA_SDA / VGA_SCL pins wire through to DE-15 pins 12 / 15. The chip can read the monitor's EDID and the host FPGA gets access to it via the HDMI DDC side — so the system can auto-configure resolutions based on what the monitor actually supports.
• Minimal FPGA pin count — 4 TMDS pairs + HPD GPIO + two I²C lines for EDID read-back. 11 pins total versus ~28 for an R-2R-ladder 5-5-5 VGA with parallel-path audio.
• Electrically separate from the main display + audio. A retro core can send different content to this port than to the main output.
• Supports native VGA resolutions (31 kHz) and "superresolution" 240p/288p tricks for genuine 15 kHz CRT output via external downstream adapters. See 240p superresolution.
• Commodity-chip path with community cable support. AG6201 is the same chip MiSTer Direct Video dongles use, so all community-known-good cables and adapters are drop-in compatible.
• Shared across any host system that adopts this port spec — Ant64 and eZX Spectrum use the same PCB sub-circuit, the same AG6201, and the same external cables / adapters.

Architecture

                                                AG6201
                                                HDMI→VGA bridge
                                                + embedded 8-bit audio DAC
 Host FPGA ──── 4× TMDS pairs ─────────────► ┌──────────────────┐
           (video + embedded audio)          │                  │─── R ───┐
                                             │   video          │─── G ───│
                                             │   path           │─── B ───│  DE-15
                                             │                  │─── HSync│  VGA
                                             │                  │─── VSync│  socket
                                             │   DDC            │─── SDA  │
                                             │   pass-through   │─── SCL  │
                                             │                  │    +5V  │
           (HDMI DDC I²C) ◄──────────────────│                  │         │
                                             │                  │         │
                                             │   audio          │─── AOUTL ──► 3.5 mm
                                             │   DAC            │─── AOUTR ──► TRS jack
                                             │                  │              (next to
           HPD ◄──────────────────────────── │                  │              DE-15)
                                             └──────────────────┘

Host FPGA pin budget: 8 TMDS + 1 HPD GPIO + 2 I²C (HDMI DDC). Adding AUDIO_EN on a GPIO for optional mute control is a 12th pin if wanted.

Audio is inherently sync'd to video because both travel in the same HDMI stream clocked off the same pixel-clock domain. No drift, no resync logic, no separate audio clock domain on the host side.

Connectors

DE-15 VGA (female, panel-mount)

Standard HD-15 VGA pinout — everything in its spec-defined position:

3.5 mm TRS audio jack (female, panel-mount, stereo)

Placed right next to the DE-15 on the back panel, standard line-out TRS stereo:

Standard "laptop audio out / projector audio in" configuration. Every 3.5 mm audio cable works.

Video subsystem

AG6201

Algoltek AG6201 HDMI 1.4b → VGA bridge with embedded audio DAC.

• QFN-48, 6 × 6 mm
• Supports 480p60 through 1920×1200p60 (HDMI TMDS minimum 25 MHz pixel clock is the lower bound)
• Crystal-less (internal reference)
• Triple 8-bit video DAC with 75 Ω drive capability
• Embedded 8-bit stereo audio DAC (output on AOUTL / AOUTR pins 22 / 20)
• HDMI and VGA DDC channels both exposed
• On-chip HDCP 1.4 (not exercised — the host does not assert HDCP)
• Dual-rail: 5 V + 3.3 V supplies
• £0.89 per chip on AliExpress in packs of 10 — commodity pricing; same silicon as most consumer HDMI→VGA dongles, same electrical spec as MiSTer Direct Video

Why AG6201 is the right default

The retro canon this port serves is dominated by machines with low-bit-depth audio:

• Spectrum beeper: 1 bit
• AY-3-8910 / YM2149 / C64 SID / NES / Atari POKEY: 4-bit volumes
• Amiga Paula, Ad-Lib / OPL2, SoundBlaster, MOD tracker: 8-bit samples

An 8-bit DAC is an exact match or an over-spec for all of the above. The only outlier in the retro canon is the SNES SPC700 (16-bit samples), and even there the perceptual gap between 8-bit and 16-bit is smaller than the raw numbers suggest because SPC700's practical dynamic range is around 11–12 bits after BRR compression. For a machine like the eZX Spectrum, the AG6201's 8-bit DAC is dramatically more than the source material needs.

Against this the AG6201 offers:

• Lowest BOM cost of any suitable bridge chip (£0.89 vs £1.50–3 for alternatives)
• Widest availability — commodity Chinese dongle chip, stocked by every AliExpress seller
• MiSTer Direct Video compatibility — same silicon as the official MiSTer HDMI→VGA dongles, meaning the entire MiSTer community's cable ecosystem, compatibility database, and known-good-settings guides apply directly
• Mature documentation from a decade of MiSTer community testing

If higher audio fidelity is wanted (for Ant64 SNES cores, Saturn, PS1, CD-era machines, or modern content), see Optional upgrade: CS5213.

Black crush mitigation

The AG6201 (like the related AG6200) clamps RGB values ≤ 16 to black. This is designed for limited-range (16–235) CEA input but causes loss of shadow detail on full-range signals.

Per the MiSTer FPGA community's empirical testing of AG6200-family DACs (documented in their Direct Video wiki), these chips don't output proper 16–235 limited range — they clip the bottom at 16 but pass the top all the way to 255, giving an effective output range of 16–255. Feeding standard 16–235 produces slightly dim whites at the analog output.

Mitigation: the host's HDMI TX output stage remaps RGB into the 16–255 window before TMDS encoding (equivalent to MiSTer's hdmi_limited=2). Black sits at code 16 with no crush; white hits code 255 for a full 0.7 V swing at the VGA connector. Cores natively producing 0–255 RGB have their values scaled by this pipeline stage.

Output levels

At the DE-15 connector, RGB outputs are 0.7 Vpp into 75 Ω, back-terminated by the AG6201. This is the VESA DMT / VGA spec level — directly compatible with every VGA monitor and multisync CRT. The output range is also safe for SCART-level circuits in downstream adapters (SCART spec is 0.7 Vpp into 75 Ω, same as VGA, with a 1.0 Vpp hard ceiling).

Any cable-maker supplying a VGA→SCART adapter should confirm the adapter was designed for a 0.7 Vpp source (most modern ones are) rather than the older 1.4 Vpp console convention. Adapters built for 1.4 Vpp sources include a 75 Ω series attenuator that would halve this port's signal down to 0.35 Vpp — dim washed-out picture. See Cables and adapters.

Hot-plug detect

HPD from the AG6201 (pin 44) is wired to a host FPGA GPIO. The host uses this to:

• Detect AG6201 lock-up and reset if necessary
• Detect monitor connect / disconnect
• Trigger EDID re-read when a new monitor is plugged in
• Optionally mute audio around mode changes via AUDIO_EN

Modelines

The AG6201 passes any valid TMDS modeline it receives. The host FPGA synthesises modelines per retro-core requirement, clamped to what the monitor's EDID (read via DDC) advertises as supported.

*Non-standard modelines — see 240p superresolution mode.

240p superresolution mode

HDMI TMDS requires a ≥25 MHz pixel clock to establish a link. Native 15 kHz 240p sits around 6.7 MHz pixel clock and cannot be carried directly. The workaround is to pad the horizontal axis with extra samples until the pixel clock clears 25 MHz, while keeping the HSync rate at 15.734 kHz (NTSC) or 15.625 kHz (PAL):

HSync rate     = 15,734 Hz   (NTSC 240p)
Pixel clock    ≥ 25 MHz       (HDMI floor)
∴ Htotal      ≥ 25 MHz / 15.734 kHz ≈ 1590

Pick Htotal   = 1716
Vtotal        = 262 lines (240 active + 22 blanking)
Pixel clock   = 1716 × 15,734 = 27.00 MHz  ✓
Refresh       = 27e6 / (1716 × 262) = 59.94 Hz  ✓

The host declares this to the HDMI encoder as e.g. 1440×240p60 with wide blanking. The AG6201 neither knows nor cares — it just DACs the RGB and passes the 15 kHz sync through. A 15 kHz CRT connected to the VGA output (either directly, for multisync CRTs that accept 15 kHz, or through a VGA→SCART / VGA→component adapter) receives normal-looking analog RGB at the retro sync rate. The "extra" horizontal samples become a finer-grained analog waveform that the CRT's dot pitch and beam focus smooth back into your real pixels with soft edges.

Each retro pixel is output as ~5–6 TMDS samples wide. Real CRT horizontal resolution is ~450–600 effective samples; the oversampling lowpass-filters naturally.

PAL 288p: swap 15,734 → 15,625 Hz, 262 → 312 lines, 59.94 → 50.00 Hz. Everything else unchanged.

Do not insert HDMI splitters, AVRs, or capture cards between the host HDMI TX and the AG6201 — they will reject the non-standard modeline. The AG6201 sits directly on the same PCB with no intermediate HDMI consumers, which is why this works.

Prior art: This technique was pioneered by the MiSTer FPGA project as their Direct Video feature (2019), using the same AG6200/AG6201 silicon. This port implements the same idea natively — the DAC is inside the machine rather than on an external HDMI dongle, but the mechanism is identical. Every compatibility finding the MiSTer community has documented — AG6200-family DAC behaviour, the 470 Ω sync resistor, the 16–255 output range, sync-on-green for YPbPr, the "do not hot-plug the DAC" rule — applies here too, and the doc cross-references theirs where relevant.

Audio subsystem

Audio is handled entirely inside the AG6201. The host FPGA inserts stereo LPCM samples into HDMI audio-island packets inside the TMDS blanking intervals (standard HDMI 1.4 feature), the AG6201 recovers those packets, and its embedded stereo DAC outputs analog line-level audio on AOUTL (pin 22) and AOUTR (pin 20). Those two pins wire — via a DC block and a small series resistor — directly to the 3.5 mm TRS jack.

No external audio DAC, no I²S routing on the PCB, no FPGA audio pins, no audio PLL on the host side. The entire audio path is inside one chip that's there anyway for video.

Why the embedded DAC is enough

The AG6201's embedded audio DAC is 8-bit. That's unglamorous by audiophile standards, but it's a remarkably good match for the use case:

• Spectrum beeper — 1-bit.
• C64 SID — 4-bit amplitude × 3 voices, analog-synthesised output.
• NES 2A03 / Atari POKEY / AY-3-8910 / YM2149 — 4-bit volume envelopes.
• Amiga Paula — 8-bit samples × 4 channels.
• Adlib / OPL2 — 9-bit internal accumulator, 8-bit effective.
• SoundBlaster / MOD tracker — 8-bit samples.
• SNES SPC700 — 16-bit samples (the one outlier where 8-bit output slightly undersells the source).

For every retro machine except the SNES, the AG6201's 8-bit DAC has equal or better resolution than the source material. The analog speaker chain after the 3.5 mm jack — the amp, the speakers, the room — is the weak link, not the DAC.

For the eZX Spectrum specifically (1-bit beeper + AY-3-8910), the AG6201 is dramatically over-spec on audio and cost-optimal. It is the canonical chip for this design.

For Ant64 running SNES-or-later cores, see the optional upgrade below if higher fidelity is wanted.

Enabling the audio DAC

Per the AG6201 datasheet, the AUDIO_EN pin (14) controls the embedded audio DAC:

• AUDIO_EN = NC (pulled high internally): audio DAC enabled.
• AUDIO_EN = GND via 1 kΩ: audio DAC disabled.

Leave AUDIO_EN floating for normal operation; the internal pull-up keeps it enabled. Optionally bring it out to a host FPGA GPIO (with a small FET or buffer) for software-controlled mute during modeline changes or cable events.

Output stage wiring

AOUTL and AOUTR from the AG6201 are internally biased, already roughly line-level. The path from AG6201 to 3.5 mm jack needs:

• 10 µF ceramic or tantalum in series on each channel — external DC block, belt-and-braces against any bias drift.
• 100 Ω series resistor on each channel — short-circuit protection if the cable shorts to ground.
• 22 pF shunt to audio GND at the connector on each channel — RF ingress filter.

Same layout on both L and R channels.

Power for the audio DAC

The AG6201's audio DAC power comes from its on-chip 3.3 V rail available on DAC_PWR (pin 19). This is driven internally by the chip's regulator — no external LDO or separate supply needed. Decouple DAC_PWR with 100 nF close to the pin.

Analog audio ground (3.5 mm jack sleeve) ties to the AG6201's VSS at the chip, with a ferrite bead connecting that point to the main board GND plane to keep audio-frequency digital noise out of the analog return. Chassis GND (DE-15 shell) ties to main board GND at the connector itself.

Optional upgrade: CS5213

For designs that want 16-bit audio fidelity for SNES-era and later content (Ant64 running SNES / PS1 / Saturn cores, CD-era audio, or modern content), the Capstone CS5213 is a higher-quality alternative. It occupies the same functional slot as the AG6201 but is not a drop-in replacement — it needs a different PCB footprint.

CS5213 vs AG6201

What CS5213 gets you

1. 16-bit sigma-delta audio DAC at 48 kHz. Full source-quality for SNES / PS1 / Saturn sample music. SNR ceiling jumps from ~50 dB (AG6201) to ~98 dB. Quiet passages that the AG6201 grains up (Chrono Trigger piano intros, Yoshi's Island ambient themes) come through clean.
2. Smaller package (4×4 vs 6×6 mm). Saves ~20 mm² of PCB area.
3. Single 5 V supply. One less rail to route.
4. Embedded EDID fallback — if the monitor has no EDID EEPROM or it's corrupt, the chip provides its own EDID to the HDMI source so the link still comes up.
5. Firmware-updatable via I²C through the embedded 8051 MCU.

What to watch for if switching

• Different footprint. Not a drop-in. Needs a separate PCB variant or a dual-footprint layout (which doesn't fit practically due to pin-count and function differences).
• AUDIO_EN polarity is inverted. CS5213 AUDIO_EN (pin 16) is active-high with an internal pull-down; tie to VDD33 via 1 kΩ for normal operation. Copying AG6201 reference schematics directly will leave audio disabled.
• Audio output labelled "headphone" in the CS5213 datasheet. AUD_L (pin 24) / AUD_R (pin 22) are driven by the headphone-capable driver; bench-measure actual Vrms into a line-level load on the prototype and add ~470 Ω–1 kΩ series on each channel if output is hotter than ~0.8 Vrms.
• AUD_VREF decoupling mandatory. CS5213 pin 23 needs 10 µF in parallel with 100 nF to analog ground, close to the pin. Without this the audio is noisy.
• Less MiSTer-community history. Compatibility with community cables is inferred-by-analogy rather than tested; any deviations in black-crush or level behaviour are your problem to debug. For production, prefer the AG6201 where the community has already done the work.

When to use which

The canonical schematic, pinout, and BOM in the rest of this document are for the AG6201.

DDC / EDID handling

One of the benefits of routing the AG6201's VGA_SDA / VGA_SCL pins through to DE-15 pins 12 / 15 is that the bridge can read the monitor's EDID when one is connected, and pass relevant fields through to the host FPGA via the HDMI DDC interface.

What the host gets:

• Monitor make, model, serial (for logging / OSD display)
• Native resolution and refresh rate
• List of supported standard modes (VESA DMT and CEA timing codes)
• Detailed timing descriptors for less-common native modes
• Colour space / range preferences
• Physical size (for aspect-ratio correction)
• Audio capability flags (though for this port audio always goes via the 3.5 mm jack)

What the host does with it:

• Clamps synthesised modelines to what the monitor supports
• Chooses a sensible default mode on cold boot (e.g., native resolution if it's ≤ 1080p, otherwise 1024×768)
• Warns the core if it requests a modeline the monitor doesn't advertise
• Can fall back to a "safe mode" (640×480@60 VGA) if EDID is missing or malformed

Wiring

AG6201 pins:

• VGA_SCL (pin 31) → DE-15 pin 15, pulled up to +5V through 2.2 kΩ
• VGA_SDA (pin 42) → DE-15 pin 12, pulled up to +5V through 2.2 kΩ
• HDMI DDC SCL (pin 46) → host FPGA GPIO (I²C clock)
• HDMI DDC SDA (pin 45) → host FPGA GPIO (I²C data)

The +5V pull-ups are powered from the polyfused +5V supplied to DE-15 pin 9 (which also powers the monitor's EDID EEPROM). 500 mA polyfuse is plenty — EDID EEPROMs draw milliamps.

HDCP

The AG6201's on-chip HDCP 1.4 engine is present but unused. The host HDMI TX does not assert HDCP, so the link stays in the clear and nothing authenticates. This is correct behaviour — no retro content is copy-protected, and exposing HDCP to the VGA output would be pointless (VGA has no HDCP path anyway).

Cables and adapters

Because the DE-15 + 3.5 mm output matches standard VGA + line-level audio at electrically identical levels to what MiSTer Direct Video dongles and the Spectrum Next VGA port produce, any cable designed for those systems works here too. This section covers both the buy-it options and DIY schematics for each retro-video destination — SCART, S-video, composite, component, BNC.

Compatible commercial cables

Any of the following work without modification:

• MiSTer Direct Video cables. Retro Access, Retro Gaming Cables, Insurrection Industries, and similar vendors sell SCART / component / S-video / BNC cables targeted at MiSTer. They're built for a DE-15 source outputting 0.7 Vpp RGB at 3.3 V TTL sync from an AG6201 — the same spec as this port. Drop-in compatible.
• Spectrum Next cables. The Spectrum Next uses the same DE-15 + 3.5 mm layout and similar signal levels, so its cable ecosystem works here.
• Generic VGA → SCART / component / S-video / BNC adapters. Off-the-shelf consumer products. Verify they're designed for 0.7 Vpp RGB (standard VGA-era spec) rather than the older 1.4 Vpp console convention, otherwise RGB levels come out halved and the picture is dim. The MiSTer community maintains a known-good list in the Direct Video wiki.
• OSSC / RetroTINK. Scaler / transcoder boxes that can consume this port's VGA output (including 15 kHz superresolution) and produce any of SCART, component, HDMI, S-video, etc. Useful for display chains that include modern TVs.

For the DIY route, the schematics below cover the same designs. All assume a VGA-shell enclosure at the source end with the 3.5 mm audio plug breaking in alongside.

DIY: VGA + 3.5 mm → SCART RGB

Active cable with a single XOR gate generating CSync from HSync ⊕ VSync, powered off the VGA connector's own +5V rail. Also uses that +5V via a 180 Ω dropper to hold SCART pin 16 at the RGB-mode detect level.

    DE-15 VGA plug (at host end)                         SCART 21-pin male

    Pin 1   Red      ─────────────────────────────────► Pin 15   Red
    Pin 2   Green    ─────────────────────────────────► Pin 11   Green
    Pin 3   Blue     ─────────────────────────────────► Pin 7    Blue

                                 74LVC1G86 XOR
    Pin 13  HSync  ─────────► A  ┌─────────┐
                                 │    ⊕    │── 470 Ω ── 1 µF ──► Pin 20  CVBS / CSync
    Pin 14  VSync  ─────────► B  └─────────┘
                                 │  VCC GND│
    Pin 9   +5V   ───┬───────────┴────┬────┘
                     │   100 nF       │
                     ══               │
                     │                │ cable GND
                     │
                     └──── 180 Ω ──────────────────────► Pin 16  Fast blanking (RGB enable)

    3.5 mm TRS plug (at host end, stereo)
    Tip     Audio L  ── 10 µF ── 10 kΩ ─────────────► Pin 6   Audio L in
    Ring    Audio R  ── 10 µF ── 10 kΩ ─────────────► Pin 2   Audio R in
    Sleeve  Audio GND ──────────────────────────────► Pins 4, 5   Audio GND

    DE-15 Shell  GND ───────────────────────────────► Pins 13, 17, 18, 21  Video/chassis GND

                                                     Pin 8   Aspect select — NC (leave floating)

Divider math: 470 Ω + SCART's internal 75 Ω termination on pin 20 gives 3.3 V × 75/(470+75) ≈ 0.45 V at the TV's sync input. Within SCART's ~0.3 Vpp video-level sync spec. 680 Ω or 750 Ω hits 0.3 V more precisely; 470 Ω is the community-standard value that works across both 3.3 V and 5 V TTL sources. This is the same resistor MiSTer Direct Video cables use.

RGB-detect math: 180 Ω + SCART's 75 Ω internal load on pin 16 gives 5 V × 75/(180+75) ≈ 1.47 V at the TV, inside the 1–3 V RGB-select window.

Parts:

• 1 × 74LVC1G86 single-gate XOR, SOT-23-5
• 1 × 470 Ω, 0603 1 % (CSync TTL → video-level divider)
• 1 × 180 Ω, 0603 1 % (+5V → SCART pin 16 dropper)
• 2 × 10 kΩ, 0603 1 % (audio level attenuation)
• 1 × 1 µF ceramic, 0805 X7R (CSync DC block)
• 2 × 10 µF ceramic, 0805 X7R (audio DC blocks)
• 1 × 100 nF ceramic, 0402 X7R (XOR VCC decoupling)
• DE-15 VGA male + 3.5 mm TRS male + SCART 21-pin male + shielded multi-conductor cable

Total active BOM: ~£0.25. Fits inside a moulded SCART shell.

Do not:

• Add 75 Ω series resistors to RGB lines. The AG6201 already delivers 0.7 Vpp through its own 75 Ω back-termination; another 75 Ω in series halves the signal to 0.35 Vpp at the TV. This is the single most common cable-build mistake for people used to older console (MD / SNES / PS1) SCART cables — those consoles output 1.4 Vpp and the cable's series R is what drops them to spec.
• Drive SCART pin 8 to +5V. Pin 8 is aspect / function; 5–8 V forces 16:9 on some TVs. Leave floating.
• Use polarised caps on audio unless you're sure of DC offset. Ceramic is simpler.

DIY: VGA + 3.5 mm → S-video (Y/C)

Active encoder chip (AD724 NTSC, AD725 PAL, or CXA1645 dual-standard) inside a small in-line enclosure. Too bulky for a moulded DE-15 shell — use a SCART-shell-sized box at the host end with a 4-pin S-video mini-DIN on a short tail.

    DE-15 VGA plug                    Encoder                      S-Video 4-pin mini-DIN

    Pin 1   Red     ────────────────► RIN
    Pin 2   Green   ────────────────► GIN
    Pin 3   Blue    ────────────────► BIN

    Pin 13  HSync  ─┐
                     │  74LVC1G86 XOR ── CSYNC_IN
    Pin 14  VSync  ─┘

                                         AD724 / AD725 / CXA1645
                                                 YOUT ─── 75 Ω ── 10 µF ──► Pin 3  Y (luma + sync)
                                                 COUT ─── 75 Ω ── 10 µF ──► Pin 4  C (chroma)
                                                                            Pins 1, 2   GND

                                         Xtal: 3.579545 MHz (NTSC)
                                            or 4.433619 MHz (PAL)
                                            or switchable (CXA1645)

    Pin 9   +5V   ──┬─────────────► VCC  (3.3–5 V)
                    │   100 nF                          ├─── GND ── chassis
                    ══                                  │
                    │
                    GND

    3.5 mm TRS  →  passes through to separate 3.5 mm jack or twin RCA on the destination end,
                   no encoder involvement. Tip = L, Ring = R, Sleeve = GND,
                   each channel AC-coupled through 10 µF.

    DE-15 Shell  GND ────────────────────────────────────────────► All shields

Current draw on VGA pin 9 (+5V):

Worst case ~60 mA, well under the 500 mA polyfuse on VGA pin 9.

Notes:

• Encoder standard (NTSC / PAL) follows the crystal. CXA1645 has a TTL standard-select pin that can be routed to a small switch on the enclosure for dual-standard operation without swapping crystals.
• Y output carries sync-on-luma; no separate sync pin on the 4-pin DIN.
• Encoder CSYNC_IN takes TTL directly. No 470 Ω between XOR and encoder — that resistor is SCART-specific.

DIY: VGA + 3.5 mm → composite (CVBS)

Same circuit as the S-video cable above, but with the encoder's CVBS output pin routed to a single RCA jack instead of separate Y and C. AD724 / AD725 / CXA1645 all have a CVBS output mode. Audio breaks out to a separate pair of RCA jacks alongside the CVBS RCA.

DIY: VGA + 3.5 mm → component (YPbPr)

Two approaches: simple passive sync-on-green (SoG) pseudo-component, or full active colour-space transcoder.

Passive SoG pseudo-component — works on monitors that accept SoG and are flexible about colour space (many consumer CRTs and some projectors). Feeds RGB directly to what would be Pb / Y / Pr, embedding sync on Y via the classic MiSTer 1N4148 + 330 Ω trick:

    DE-15 VGA plug                                         3× RCA (component out)

    Pin 2   Green   ──┬──── 10 µF ────────────────────► Y  RCA (tip)
                      │
    Pin 13  HSync  ──►│     1N4148
                      │     ───▶├─── 330 Ω ──── (sync-on-luma into Y line)
    Pin 14  VSync  ──►│          (or compose CSync from H⊕V first,
                      │           drive the diode from CSync only)
                      │

    Pin 1   Red    ──────── 10 µF ────────────────────► Pr RCA (tip)
    Pin 3   Blue   ──────── 10 µF ────────────────────► Pb RCA (tip)

    DE-15 Shell  GND ─────────────────────────────────► All RCA shields

    3.5 mm TRS audio → twin RCA
    Tip    ── 10 µF ──► L audio RCA
    Ring   ── 10 µF ──► R audio RCA
    Sleeve ─────────── Audio shields

Caveats: This is colour-space-incorrect — true YPbPr uses a 0.299 R + 0.587 G + 0.114 B matrix with colour-difference encoding, which this passive cable doesn't do. Most monitors accept it with hue/tint adjustment; some refuse or show green/magenta casts. If you need proper YPbPr, use an active transcoder (THS7374, SAA7127, or an OSSC / RetroTINK in passthrough mode) instead.

Active transcoder — same general cable topology, but with a THS7374-class IC in-line that does the RGB → YPbPr matrix properly. Powered from VGA pin 9 +5V, draws ~40 mA. Recommended for picky monitors.

DIY: VGA + 3.5 mm → BNC (PVM)

For Sony PVM / BVM broadcast monitors. Simple passive breakout — no active parts unless you need CSync generation for RGBS-only PVMs.

    DE-15 VGA plug                                    BNC connectors

    Pin 1   Red    ───── 75 Ω coax ──────────────► Red BNC
    Pin 2   Green  ───── 75 Ω coax ──────────────► Green BNC
    Pin 3   Blue   ───── 75 Ω coax ──────────────► Blue BNC

    OPTION A — RGBHV (PVM accepts separate H/V inputs):
    Pin 13  HSync ─────────────────────────────► HSync BNC
    Pin 14  VSync ─────────────────────────────► VSync BNC

    OPTION B — RGBS (PVM accepts composite sync only):
    Pin 13 ──┐ XOR (powered from VGA pin 9 +5V)
             ├── 470 Ω ── 1 µF ─────────────────► Sync BNC
    Pin 14 ──┘           (video-level into PVM's 75 Ω termination)

    Shell  GND ─────────────────────────────────► All BNC shields

    3.5 mm TRS audio → twin RCA or dedicated speaker amp input,
                       passthrough with 10 µF DC blocks per channel.

Cable construction: use proper 75 Ω shielded coax per colour channel (RG-179 or equivalent for flexibility, RG-59 for runs >1 m). Don't use ribbon cable — impedance mismatch causes ghosting at VGA pixel rates.

Historical note: MD2 connector

An earlier revision of this spec proposed an MD2-style 9-pin mini-DIN with a custom pinout, to combine video and audio on one connector and carry +5V for active cables. That approach was abandoned in favour of standard DE-15 + 3.5 mm because the custom-cable complexity outweighed the space saving, especially when third-party VGA→SCART adapters already exist and are well-supported. The MD2 pinout is documented in the project history but is not the current spec.

Why HDMI + DAC instead of a resistor ladder

Earlier iterations of this port considered an R-2R resistor ladder giving 5-5-5 RGB (15 bits = 32 768 colours) straight from FPGA pins, with separate HSync/VSync/CSync digital outputs. The HDMI → AG6201 path was chosen instead, and this is worth explaining because the ladder approach is the "obvious" answer for a simple retro RGB port and looks cheaper on paper.

Colour depth. 5-5-5 gives 32 levels per channel; a step is 700 mV / 32 ≈ 22 mV. 24-bit via AG6201 gives 256 levels per channel and a step of 2.7 mV. Gradient banding is invisible at 8 bits per channel and extremely visible at 5 — you see it on sunset skies, smooth-dithered images, emulated CRT glow gradients, and anywhere colour transitions slowly across a surface. Going to 6-6-6 VGA (64 levels per channel) helps but doesn't eliminate it. Once an eye is used to 8-bit colour, 5-bit or 6-bit feels obviously wrong.

Pin budget.

The HDMI path cuts FPGA pin count to roughly half the cheapest ladder option.

Image stability. This is the argument that really settled it.

An R-2R ladder's output voltage is determined by the FPGA's pin Vcc rail and the resistor divider ratios. That voltage drifts with:

• Temperature — die self-heating during operation shifts bank Vcc by tens of mV; resistor tolerance adds thermal coefficient drift on top.
• Supply noise — switching regulator ripple, activity on adjacent digital pins on the same bank, and ground bounce from other I/O all couple into the pin output voltage. FPGA datasheets typically quote ±50–100 mV of SSO-induced bank-Vcc deviation under worst-case switching. At 22 mV/step for 5-5-5, that's two to five LSBs of noise on every colour.
• Ground bounce — the package and PCB ground reference shifts by millivolts when many pins switch simultaneously, shifting the apparent output voltage relative to the monitor's ground reference by the same amount.
• Pin-to-pin mismatch — each R-2R output has slightly different parasitic capacitance (via-to-plane, trace length) so edges don't align perfectly between colour channels. You get tiny colour fringing on sharp transitions, worse at higher pixel clocks.

The visible symptom is a picture that's almost stable — colours shimmer subtly, solid areas show faint noise, gradients have a ghostly "crawling" texture. It's a well-known MiSTer-era artefact; it's why the official MiSTer I/O board uses a proper ADV7125 DAC instead of GPIO resistors. On a cheap I/O board with an R-2R ladder, the difference is obvious even on casual viewing.

TMDS → AG6201 doesn't have any of these problems. The analog voltages are generated inside the AG6201 by a dedicated 8-bit current-steering DAC with its own bandgap voltage reference, its own analog ground, and its own output buffer. The FPGA side is pure digital TMDS — FPGA supply noise can't reach the analog output because there is no analog output on the FPGA. The worst that FPGA supply/ground noise can do is induce TMDS bit errors, and TMDS is clocked at 10× the pixel rate with self-synchronous recovery that tolerates hundreds of picoseconds of jitter. At 25–165 MHz pixel rates (250–1650 Mbps TMDS), we have 6+ ns jitter margin. FPGA digital noise that would clearly mangle a 22 mV R-2R step isn't even visible as TMDS jitter.

Layout and EMC.

Cost. AG6201 is remarkably cheap — AliExpress has them at £0.89 each in packs of 10 (£8.89 / 10), and volume pricing drops further. A precision 0.1 % resistor R-2R ladder with 3 × 15 = 45 resistors plus sync buffering comes out to roughly £0.60–1.00 in resistors alone, before you add an external DAC (ADV7125-class, ~£3–4) if you want anything better than 6-6-6. Net BOM cost of the AG6201 path is cheaper than a proper R-2R ladder, and dramatically cheaper than any dedicated external DAC.

Audio is free. The AG6201 includes an embedded audio DAC that would otherwise need a separate chip (PCM5102A or similar, ~£1.50) in the ladder approach — plus the LDO and decoupling parts around it, several more FPGA pins, and a separate clock domain. With the AG6201, audio arrives embedded in the HDMI stream and exits as analog L/R with no extra parts on the board.

Resolution ceiling.

What you give up. Two things:

1. HDMI's 25 MHz TMDS floor means native 240p at 6.7 MHz doesn't fit. You use the superresolution trick instead (described earlier), which works but adds some conceptual complexity.
2. The AG6201's black-crush behaviour (16 = black). Mitigated by the 16–255 remap, but it's a real thing you have to handle in firmware.

Both are well-understood, documented by the MiSTer community, and trivially fixable in the host's HDMI output pipeline. Against that, you get:

• 8-bit-per-channel colour (16.7 M vs 32 K)
• Rock-solid image stability independent of FPGA digital activity
• Free audio DAC in the same chip
• Roughly half the pin count
• Much simpler PCB layout
• Better EMC behaviour
• Higher maximum resolution
• DDC support for monitor EDID
• A replaceable analog stage if the output ever fails

For a modern retro-oriented machine that also wants a real HDMI output, this is an easy decision.

Bill of materials

Host-side (mainboard):

Approximate BOM cost: ~£1.50 per machine for the retro port (AliExpress pricing: AG6201 at £0.89 in packs of 10, plus connectors and passives, excluding PCB area). Volume pricing from Algoltek distributors (via LCSC or a rep) is higher per-unit than AliExpress small-quantity but comes with factory-sealed dry-pack parts and lot traceability — recommended for commercial production.

If using the CS5213 upgrade instead: add ~£1 for the chip (£1.50–3 vs AG6201's 89p), plus the mandatory AUD_VREF 10 µF + 100 nF bypass (~£0.02) and the AUDIO_EN pull-up resistor (~£0.01). Total BOM ~£2.50 for the CS5213 variant.

Host FPGA integration requirements

Any host system implementing this port needs:

• 1 × secondary HDMI TX — 4 LVDS TX-capable differential pairs to route TMDS to the AG6201. Pixel clock range 25 MHz (480p60 floor — superresolution uses this) to ~165 MHz (1080p60, inside the AG6201's range). HDMI audio-island packet insertion must be supported by the host's HDMI IP (standard feature on every modern HDMI TX core).
• 1 × GPIO input — HPD from the AG6201 (pin 44).
• 2 × I²C GPIOs — HDMI DDC (SDA/SCL) between host and AG6201 (pins 45 / 46), for EDID readback.
• 1 × optional GPIO output — AUDIO_EN control for mute around mode changes.
• 1 × pixel PLL — may be shared with the primary HDMI TX if they run the same modeline; usually they don't, since the retro port often runs superresolution or 480p while the main port runs 1080p or 4K.
• Total FPGA pin cost: 8 differential TMDS + 3–4 single-ended GPIOs = 11–12 pins.

No audio PLL, no I²S master, no external audio DAC. Audio sample timing is embedded in HDMI audio-island packets and reconstructed inside the AG6201.

Minimum FPGA class

This port works on any modern FPGA family with two HDMI TX outputs and two PLLs — entry-level parts from GoWin (GW2A series and up, GW5A series), Lattice (CrossLink, ECP5), Xilinx (Artix-7), Altera (Cyclone V), and Efinix (Trion) all have enough headroom. The TMDS rates needed (up to 1.65 Gbps per pair for 1080p60) are modest by current standards.

For a host already driving one HDMI output at 1080p60, adding this port typically uses LVDS banks and PLLs that are already instantiated for other purposes. No dedicated high-speed SerDes is required — standard LVDS I/O on a 3.3 V bank with appropriate termination is sufficient for TMDS at sub-2 Gbps rates.

Architecture note for eZX Spectrum (GW5A-60K): this host uses its SerDes transceivers for the main 4K@60 HDMI output via a Parade PS176 DP→HDMI bridge (see hdmi_out). The retro VGA port described here runs off regular fabric-pin LVDS at the lower TMDS rates appropriate for VGA modelines, leaving the high-speed SerDes free for the main output path. This is a deliberate pin-budget allocation.

AliExpress sourcing notes

The AG6201 is a commodity part in thousands of consumer HDMI-to-VGA dongles, which is why it's so cheap. It also means there are some sourcing realities to be aware of:

• Fakes and relabels. The AG6201 is cheap enough that outright fakes are uncommon, but relabelled AG6200 (video-only, no audio DAC) sometimes surfaces sold as "AG6201". If audio doesn't work on a built board, probe AUDIO_EN (pin 14) and AOUTL/AOUTR (pins 22/20) for activity; an AG6200 in AG6201 clothing will show nothing on those pins.
• Lot variation. Algoltek have revised the AG6201 die at least twice. Earlier silicon has slightly different black-crush behaviour than later silicon — documented by the MiSTer community. The hdmi_limited=2 (16–255) remap specced here works on all revisions, but if you buy two batches of chips from different AliExpress sellers you may see small output-level differences. For a single production run, buy all the chips from one seller at once.
• Moisture sensitivity. QFN parts stored in non-sealed bags for months can absorb moisture and delaminate during reflow. For a prototype run it's not a problem, but for a production batch bake the parts at 125 °C for 24 hours before placement, or ask the seller for factory-sealed dry-pack.
• Buy spares. At 89p each, get 20–30 even for a single prototype — reworking a 48-pin QFN out of a PCB is painful, and a spare tube means throwing the first mistake away and popping a new one on.

For a commercial product with traceable supply, go through LCSC, Mouser, or an Algoltek rep instead of AliExpress. Expect £1.50–2.00 per chip at that level but with authenticity guarantees, lot date codes, and proper dry-pack storage.

Prototype validation checklist

When the first board is up:

1. Verify chip identity. Check the AG6201 marking; probe AUDIO_EN (pin 14) high and AOUTL/AOUTR (pins 22/20) for signal activity when HDMI audio is being fed. An AG6200 relabel will have no audio.
2. Characterise black-crush behaviour. Feed a staircase ramp from code 0 to code 255 via HDMI; verify the output clips at 16 (expected) and that code 255 reaches full 0.7 V swing. Confirms hdmi_limited=2 is the right host setting.
3. Verify 240p superresolution. Generate a 1440×240p60 mode at 27 MHz and confirm the VGA output is 15.734 kHz horizontal / 59.94 Hz vertical on a scope. Plug into a real 15 kHz CRT through a SCART adapter to confirm picture.
4. Test EDID readback. Plug in a known-good monitor and read EDID through the HDMI DDC path from the host FPGA.
5. Measure audio output amplitude. AOUTL / AOUTR should deliver ~1 Vrms at full-scale tone into a 10 kΩ line load. Significantly different levels suggest layout or AUDIO_EN wiring issues.
6. Check hot-plug behaviour. Unplug and replug the VGA cable while the host is running; confirm HPD toggles on the host GPIO and that sync re-establishes cleanly.

Known issues and caveats

• AG6201 black crush on RGB ≤ 16. Mitigated by 16–255 output range remap in the host HDMI TX. Document this clearly for core developers.
• Superresolution compliance. Direct-to-AG6201 only — no intermediate HDMI sinks tolerated. The secondary HDMI output is internal to the PCB, not user-accessible, so this is enforced by layout.
• Hot-plug click. Plugging/unplugging a VGA cable while the system is running can cause a brief audio click on the 3.5 mm output as the AG6201's sync-loss detection fires. Acceptable for retro use; can be soft-muted via the AUDIO_EN pin if a host GPIO is wired.
• Ground loop risk with external SCART adapters. SCART TVs and the host power supply may be on different mains phases / earths. If hum is reported, users should use an isolated PSU or a ground-lift adapter on the audio lines. Not a port design flaw per se.
• DDC 5 V load. DE-15 pin 9 supplies +5 V for the monitor's DDC EEPROM, limited by a 500 mA polyfuse. Monitors draw milliamps for EDID, but ancient VGA CRTs occasionally pulled more (up to 100 mA for sync-on-green bias on some models). The 500 mA limit covers both and also protects against pin shorts.
• No audio on VGA. Some consumer devices expect audio alongside VGA on a single cable (e.g., laptops with VGA + 3.5 mm breakout, projector combo cables). The 3.5 mm jack is placed adjacent to the DE-15 so a standard "VGA + 3.5 mm" combo cable works naturally. Cables with integrated VGA+audio in one moulded shell are widely available.

Links

• MiSTer Direct Video wiki — the prior-art reference. Every electrical and timing decision in this port matches MiSTer's approach; community-documented compatibility with monitors, SCART adapters, and CRTs carries over.
• MiSTer CRT guide — practical advice on using retro CRTs with HDMI-to-VGA DAC outputs.
• Algoltek AG6201 datasheet — chip reference.
• Capstone CS5213 datasheet — upgrade chip reference.
• hdmi_out — sibling doc for the main 4K@60 HDMI output via PS176 DP→HDMI bridge (eZX Spectrum architecture).