Main HDMI Output (DP → HDMI via PS176)

The main display output on the eZX Spectrum (and as an architectural option on other hosts with DP-capable SerDes) is 4K@60 HDMI, delivered via a DisplayPort link from the FPGA's SerDes transceivers into a Parade PS176 DisplayPort → HDMI 2.0 protocol converter on the PCB. The PS176 output drives a standard HDMI Type A connector on the back panel.

This path is separate from the retro VGA port, which uses regular fabric-pin LVDS to drive an AG6201 HDMI→VGA bridge. The two ports coexist on the same board, serve different purposes, and share no silicon.

Why DP from the FPGA instead of HDMI?

Modern FPGA SerDes transceivers are natively designed around DisplayPort electrical signalling rather than HDMI TMDS. A few reasons this matters:

• Lane structure. DP uses 4 independent SerDes lanes each running at a link rate (1.62 / 2.7 / 5.4 / 8.1 Gbps). HDMI 2.0 uses 3 TMDS data lanes plus a dedicated clock lane. FPGA SerDes natively fit the DP model; HDMI requires synthesising a separate clock line alongside the data lanes which wastes a transceiver.
• Encoding. DP uses 8b/10b (and 128b/132b for DP 2.0) with AC-coupling and training patterns — exactly what SerDes blocks implement in hardware. HDMI TMDS is a specific 10-bit encoding that some SerDes can do natively and others can't. Going through DP and letting the PS176 handle the HDMI encoding decouples the FPGA choice from HDMI-specific SerDes features.
• DP is AC-coupled over link rate, simpler termination design on the FPGA side.
• Mode flexibility. With the PS176 handling the HDMI side, you get HDMI 2.0 features (4K@60 4:4:4, deep colour, SCDC, HDCP 2.3) essentially for free from the bridge's silicon, without needing to implement them in FPGA logic.
• HDCP offload. The PS176 has HDCP 1.4 + 2.3 repeater keys on-chip. Even if unused (retro content is unprotected), it future-proofs the design for cases where HDCP-protected content would flow through (streaming cores, modern OS in an Ant64 host, etc.).

On the GW5A-60K in the eZX Spectrum specifically, this allocation frees the fabric-pin I/O for other things (retro VGA, Colony Connection, peripheral I/O) while the transceivers do the high-rate display work they were designed for.

Architecture

                                            PS176
                                            DP→HDMI 2.0
                                            protocol converter
                                            + jitter cleaning PLL
                                            + HDCP keys
                                            + on-chip 8051 MCU
 Host FPGA ─── DP ML0 ±    ───────────────►┌──────────────────┐
  (SerDes    ─── DP ML1 ±    ───────────────►│                  │──── TMDS D0 ± ──┐
   transceivers,              4 DP lanes     │                  │──── TMDS D1 ± ──│
   AC-coupled   ─── DP ML2 ±    ────────────►│                  │──── TMDS D2 ± ──│
   100 nF)     ─── DP ML3 ±    ────────────►│                  │──── TMDS CK ± ──│
                                             │                  │                 │   HDMI Type A
           DP AUX CH ± ◄──── I²C over AUX ──►│                  │──── CEC ────────│   (female,
                                             │                  │──── HDMI DDC    │    back panel)
                                             │                  │      SDA / SCL ─│
           DP HPD   ◄──────── HPD status ────│                  │──── HPD ────────│
                                             │                  │──── +5V ────────│
           I²C slave                         │                  │                 │
           CFG_SDA ◄──────── optional ───────│  SPI ROM bus ────┼─── (internal,
           CFG_SCL ◄─────── control I²C  ────│                  │     no external
                                             │                  │     SPI flash
           PWR 3.3V I/O ─────────────────────│                  │     needed)
           PWR 1.2V core ────────────────────│                  │
                                             │                  │
                                             │   27 MHz xtal ───│   (or external
                                             │                  │    crystal / ref clk)
                                             └──────────────────┘

Host FPGA pin budget: 4 DP differential pairs (8 single-ended SerDes pins, AC-coupled) + 1 DP AUX pair + 1 HPD GPIO = 11 pins from the SerDes/GPIO allocation. Optional I²C control and reset to the PS176 is another 2–3 pins if the host wants to talk to the PS176 directly (usually not needed — the PS176 auto-configures from its internal ROM).

PS176 chip summary

Parade Technologies PS176 DisplayPort 1.2a → HDMI 2.0 protocol converter.

• QFN-48, 6 × 6 mm, RoHS halogen-free
• DP input: 1 / 2 / 4 lanes at 1.62 / 2.7 / 5.4 Gbps (RBR / HBR / HBR2)
• Accepts DP 1.1a, 1.2a, 1.3, 1.4 input formats (DP 1.3/1.4 at HBR2 rates only — no HBR3)
• HDMI 2.0 output up to 6.0 Gbps per TMDS channel (18 Gbps total)
• Resolution: up to 4096 × 2160 @ 60 Hz with 24-bit colour and 4:4:4 subsampling (using 4 lanes @ HBR2)
• Supports 1080p @ 120 Hz with 3D video formats
• Deep colour: RGB / YCbCr 4:4:4 / 4:2:2 at 6 / 8 / 10 / 12 bits-per-component
• YCbCr 4:4:4 / 4:2:2 → 4:2:0 conversion on-chip (for HDMI 2.0 4K@60 4:2:0 output mode)
• Audio: input and output formats include 8-channel LPCM, compressed audio (AC-3, DTS), and HBR audio; 16 / 20 / 24-bit sample size; 32 / 44.1 / 48 / 88.2 / 96 / 176.4 / 192 kHz sample rate
• HDCP: 1.4 and 2.3 repeater function with integrated on-chip Rx and Tx keys
• Jitter cleaning PLL for wide HDMI compliance margin
• On-chip 8051-class MCU with internal SPI ROM for configuration and microcode (field-updatable via DP AUX channel or device I²C slave)
• Internal crystal oscillator — supports optional external crystal or reference clock
• CEC support through dedicated HDMI receptacle pin
• SCDC (Status and Control Data Channel) for HDMI 2.0 link management
• TMDS scrambling for EMI/RFI reduction
• ESD: 7 kV HBM
• I²C master interface for external EDID (if needed) and expansion
• I²C slave interface for system control from the host
• CEC-Tunneling-over-AUX per DP 1.3 standard
• Power: 1.2 V core + 3.3 V I/O
• Power consumption:
  • Normal operation (4 lanes @ 5.4 Gbps → HDMI 5.94 Gbps): ~432 mA @ 1.2 V + ~19 mA @ 3.3 V = ~580 mW
  • Standby (DPCD 600h = 02h): ~17 mA @ 1.2 V + ~16 mA @ 3.3 V = ~73 mW
  • Auto power-down: ~70 µA @ 3.3 V only = 0.23 mW
  • PDB asserted (hard power-down): ~30 µA @ 3.3 V = 0.1 mW

Availability and pricing

• LCSC: ~$3.09 / £2.50 per chip, in stock
• Parade distributors (Macnica, Mouser equivalents): traceable supply, lot date codes
• AliExpress: less common than commodity dongle chips; availability variable

Unlike the AG6201 (a commodity Chinese HDMI dongle chip), the PS176 is a proper Western-vendor silicon with full datasheet access, stable sourcing, and commercial-grade support. Recommended for any design intended for production.

Power rails

The PS176 needs two supplies:

VDD33 — 3.3 V I/O — 2 pins (1, 24). Supply current ~19 mA typical at full load. VDDRX12, VDDA12, VDD12, VDDTX12 — 1.2 V cores/analog — 6 pins total (11, 6, 30, 15, 18, 46). Supply current ~432 mA typical at full load.

Both rails should be filtered from the main board supplies with bulk + decoupling caps local to the package. The 1.2 V rail is the dominant consumer — use a dedicated 1.2 V LDO or buck with enough headroom (500 mA rating minimum, prefer 1 A).

Power sequencing: datasheet requires 3.3 V to rise before (or simultaneously with) 1.2 V. A simple RC-delay on the 1.2 V enable, or a small power-sequencing IC (TI TPS3808 family, or similar), handles this. Most modern multi-rail PMICs do this automatically.

Decoupling: 100 nF per supply pin, placed close to the package. Add a 10 µF bulk cap per rail at the package. Exposed pad grounds to the main GND plane through multiple vias.

Reference clock

The PS176 has an internal crystal oscillator with an optional external crystal or reference clock input. Parade's reference designs typically use a 27 MHz crystal on the designated pins with small loading caps (15–22 pF typical), or a 27 MHz reference clock from an external source if the host already has a stable 27 MHz tick available.

For the eZX Spectrum, the FPGA already has several PLLs producing pixel-rate clocks; if 27 MHz is one of them, feeding it to the PS176's external reference input saves the crystal. Otherwise, a standard 27 MHz SMD crystal (e.g., Abracon ABM3B-27.000MHZ or similar, ~£0.30) is the simplest approach.

DisplayPort link

The FPGA drives 4 DP main link lanes plus the AUX pair into the PS176's DP receiver block:

• Main link lanes: 4 × differential pairs, AC-coupled (100 nF series caps, one per wire, so 8 caps total). The PS176 has internal termination (100 Ω differential, nominal).
• Link rates supported: 1.62 Gbps (RBR), 2.7 Gbps (HBR), 5.4 Gbps (HBR2). For 4K@60 4:4:4 24-bit the math requires 4 lanes at HBR2.
• AUX channel: 1 × differential pair, AC-coupled. Used for link training, EDID readback from the HDMI sink, HDCP authentication (if used), and CEC tunnelling (DP 1.3 feature).
• HPD: single-ended, 3.3 V logic. The host FPGA monitors this to detect downstream HDMI sink state — when a user plugs/unplugs a TV, HPD on the DP side reflects that.

Why 4K@60 needs 4 lanes at HBR2

Video data rate for 4K@60 RGB 4:4:4 8-bit:

3840 × 2160 × 60 Hz × 24 bits/pixel × 1.25 (8b/10b overhead) = 14.93 Gbps

Split across 4 lanes: 3.73 Gbps per lane. The nearest DP link rate above that is HBR2 (5.4 Gbps), so 4 lanes @ HBR2 works. 4 lanes @ HBR (2.7 Gbps) = 10.8 Gbps total isn't enough; 2 lanes @ HBR2 = 10.8 Gbps isn't enough either.

For 1080p60 or lower, fewer lanes or lower rates suffice:

• 1080p60 RGB 8-bit ≈ 3.73 Gbps total → 2 lanes @ HBR (5.4 Gbps aggregate) comfortably
• 1080p120 or 1440p60 → 4 lanes @ HBR or 2 lanes @ HBR2
• 4K@30 → 4 lanes @ HBR

The PS176 does link training and picks the lowest link rate that fits the sink's EDID claim, so if the connected TV is only 1080p the link falls back to HBR automatically.

SPI ROM and the on-chip MCU

The PS176 contains an 8-bit 8051-class microcontroller that runs the protocol conversion firmware. This is what makes the chip "anonymous automatic operation" — you power it up, and it just works.

Where the firmware lives is the slightly ambiguous bit in the datasheet:

• Parade's product page says "internal SPI ROM" — firmware baked into silicon, no external component needed.
• The LCSC datasheet excerpt says "The device can be configured with an SPI Flash for customized applications" — suggesting an optional external SPI flash for customised firmware.

The most likely interpretation is:

• Default firmware runs from internal ROM. For standard "DP in, HDMI out, use the downstream EDID" behaviour, no external parts are needed.
• External SPI flash can be wired to the PS176's SPI interface if you want custom firmware (e.g., a custom EDID override, boot splash through the chip, etc.). Most designs don't need this.

Recommendation: Don't populate an external SPI flash unless you have a specific reason. The internal ROM handles the standard DP→HDMI protocol conversion. Leave footprint for an external SPI flash on the PCB as DNP (Do Not Populate) in case a future firmware update is needed.

The firmware is field-updatable through the DP AUX channel or via the I²C slave interface — this means even without an external flash, custom firmware can be loaded into the chip at runtime if needed. This is how HDCP key updates and bug fixes are deployed on commercial DP→HDMI products.

Audio handling

Audio is embedded in the DisplayPort main link as audio stream packets (per the DP spec) and emerges embedded in the HDMI stream as audio-island packets (per the HDMI spec). No separate audio path, no external audio DAC, no I²S or S/PDIF pins on the PS176.

The FPGA inserts audio samples into the DP stream via its SerDes IP. The PS176 receives, buffers, repackages for HDMI timing, and outputs. Sample rate, bit depth, channel count are all preserved end-to-end (32 kHz through 192 kHz, 16 / 20 / 24-bit, up to 8 channels LPCM or HBR).

For the Ant64's FireStorm audio engine (128-voice fixed-point, 48 kHz target sample rate, 16-bit): exits the FPGA as 48 kHz stereo LPCM embedded in DP, passes through the PS176 unchanged, emerges as 48 kHz stereo LPCM in the HDMI output stream for the TV / AVR to decode. No quality loss at any stage.

Compressed bitstreams (AC-3, DTS, Dolby TrueHD via HBR) also pass through — useful for modern applications even though retro content doesn't need them.

I²C control and EDID

The PS176 has two I²C interfaces:

• I²C slave (for system control from the host FPGA). Optional — the chip runs autonomously from its ROM by default. The slave interface lets a host override defaults, read status, configure non-default modes.
• I²C master (for external EDID EEPROM or expansion ICs). The PS176 reads the downstream HDMI sink's EDID via the HDMI DDC channel directly; the I²C master is mostly useful if you want to present a custom source-side EDID to the DP input (unusual for FPGA-driven designs where the FPGA already controls what modelines it sends).

For the eZX Spectrum architecture: the FPGA reads the HDMI sink's EDID through the DP AUX channel's embedded I²C-over-AUX feature. The PS176 bridges AUX transactions to the HDMI DDC transparently. No separate DDC wiring from the FPGA to the PS176 is needed beyond the AUX pair.

HDCP

PS176 supports HDCP 1.4 and HDCP 2.3 repeater mode with on-chip keys. This means the chip can relay HDCP-encrypted content from a DP source to an HDMI sink while performing the authentication protocol.

For retro content, HDCP is not used. The FPGA does not assert HDCP on the DP input, so the HDMI output stays in the clear, and no authentication happens between the PS176 and the TV. This is correct — retro content is not copy-protected and enabling HDCP would only create compatibility issues with cheap HDMI capture gear.

For future-proofing: if the host machine ever runs commercial streaming apps or similar HDCP-protected content (Ant64 might conceivably), HDCP can be turned on via the PS176's I²C configuration without changing the hardware. The keys are already in the chip.

HDMI physical output

The PS176's TMDS output pairs (D0±, D1±, D2±, Clk±) drive a standard HDMI Type A female connector on the back panel.

• ESD protection: place TVS arrays (e.g., TI TPD4E05U06 or similar HDMI-specific ESD arrays) between the TMDS pairs and the HDMI connector. Most HDMI connectors include some ESD tolerance but external TVS is recommended for robustness.
• Common-mode chokes: optional on each TMDS pair for EMC, depending on cable length expectations and enclosure shielding. Murata DLP11S series or similar at ~0.5 Ω DCR, placed between PS176 and connector.
• CEC: single-ended line from PS176 to HDMI connector's CEC pin, 3.3 V TTL. Weak pull-up (27 kΩ) to 3.3 V per the HDMI spec.
• HDMI DDC SDA/SCL: internal to PS176 → HDMI DDC pins on the connector. 2.2 kΩ pull-ups to 3.3 V at the chip.
• +5 V to HDMI pin 18: from the board's 5 V rail through a 500 mA polyfuse. Powers the HDMI sink's EDID EEPROM and HDCP chip (if any). Should not be drawn from the PS176's own 3.3 V rail — keep the output rail clean.
• HPD from HDMI connector back to PS176's HDMI HPD input — lets the chip detect cable plug / unplug events.

Bill of materials

Host-side (mainboard):

Approximate BOM cost: ~£4–5 per machine for the main HDMI output path (excluding PCB area and the 1.2 V supply if shared with other rails).

Compare with the retro VGA port at ~£1.50 — the main HDMI output is substantially more expensive per port, reflecting the HDMI 2.0 + DP receiver + HDCP keys + microcontroller all integrated in the PS176. Worth it for 4K@60 capability.

Host FPGA integration requirements

For the eZX Spectrum (GW5A-60K) specifically:

• 4 × DP SerDes transceiver lanes, each rated HBR2 (5.4 Gbps). The GW5A-60K's transceivers need to cleanly drive these rates. Verify on datasheet — GW5A transceivers are typically rated to 6.25 Gbps but check for derating at -40°C to +85°C if the target use case spans that range.
• 1 × DP AUX differential pair — AUX is a bidirectional Manchester-encoded 1 Mbps link. Can be implemented via LVDS TX + LVDS RX on a regular LVDS bank, with external AUX isolation caps.
• 1 × HPD GPIO input — 3.3 V tolerant.
• Optional: 2 × I²C GPIOs to talk to the PS176's slave interface. Usually not needed.
• Optional: 1 × GPIO output to PS176's PDB (power-down) pin for hard reset / deep sleep.
• 1 × 27 MHz source either from a dedicated crystal on the PS176 itself, or from the FPGA's PLL network (one FPGA-fabric pin).

Total FPGA pin cost: ~11 pins (4 DP lanes × 2 + 1 AUX × 2 + 1 HPD = 11 differential-equivalent signals), all routable through LVDS/SerDes-capable banks. With optional I²C and PDB it's 13–14 pins.

PLL allocation: the FPGA needs a PLL producing the DP pixel clock (e.g., 594 MHz for 4K@60). The SerDes transceiver block contains its own PLL for the link rate; a pixel-clock PLL in the fabric feeds the DP TX IP's video-sampling logic.

Why not HDMI directly from the FPGA?

On the eZX Spectrum, yes — technically the GW5A-60K could emit HDMI TMDS directly from its SerDes transceivers if its silicon supports TMDS signalling. But:

• TMDS is 3 data lanes + 1 dedicated clock lane (4 lanes total), not 4 data lanes like DP. This wastes one transceiver since HDMI's clock lane is just a single-rate continuous clock.
• HDMI 2.0 at 4K60 4:4:4 needs 6 Gbps per TMDS channel, vs DP HBR2 at 5.4 Gbps per lane. The DP path is actually easier for SerDes to drive.
• HDCP, EDID, CEC, SCDC logic all need implementing in FPGA fabric if going direct. The PS176 bundles all of this.

So the DP-then-PS176 path is shorter in FPGA logic terms, fits the transceiver architecture better, and lets the chip handle the HDMI complexity.

Prototype validation checklist

When the first board is up:

1. Verify PS176 power sequencing. Scope VDD33 and VDD12 on power-up — 3.3 V must rise before 1.2 V. If 1.2 V comes up first, the chip may latch up.
2. Verify current draw. At idle (no DP link) expect <100 mA on 1.2 V. At 4K@60 full link, expect ~432 mA on 1.2 V + ~19 mA on 3.3 V. Large deviations suggest thermal or sequencing problems.
3. DP link training. With a simple test pattern from the FPGA, scope the DP AUX channel during link training to confirm the PS176 is negotiating a valid link rate. A logic analyser capture of AUX traffic shows DPCD reads/writes.
4. EDID readback. Connect an HDMI TV, and from the FPGA's DP TX IP, read the downstream EDID via I²C-over-AUX. Confirm the returned EDID matches what the TV reports directly.
5. Picture at increasing resolutions. Start at 640×480p60 (simple, low-rate), then step up: 1080p60, 1440p60, 4K@30, 4K@60. Each step exposes a different part of the link — if 4K@60 fails but 4K@30 works, look at HBR2 link training and PS176 power.
6. Audio A/V sync. Feed a test pattern with audio clicks timed to video frame transitions; record the HDMI output and check alignment to within a few milliseconds. PS176 doesn't introduce meaningful A/V skew but this catches FPGA-side audio-insertion bugs.
7. HDCP path (if ever needed). Probe HDCP authentication handshake via AUX with a HDCP-demanding source or test fixture. Skip if HDCP is unused.
8. Hot-plug behaviour. Unplug and replug the HDMI cable several times; confirm HPD toggles cleanly on the FPGA GPIO and link re-establishes within a few hundred ms.
9. Thermal check. After 30 minutes of 4K@60 operation, check PS176 package temperature. Should stay below 60°C in a normally ventilated enclosure. Higher temperatures suggest inadequate copper pour on the exposed pad or insufficient airflow.

Known issues and caveats

• Power sequencing is mandatory. Getting 1.2 V up before 3.3 V can latch the chip or cause persistent damage. Use a proper sequencing solution.
• DP AUX is finicky. AUX at 1 Mbps Manchester encoding with strict timing requirements. If the FPGA's AUX IP isn't spec-correct, link training fails silently — no obvious error, just no picture.
• HBR2 PCB routing. DP lanes at 5.4 Gbps need controlled-impedance differential routing (100 Ω), matched lengths within a pair (skew < 5 mil), and careful via design. Not hard, but not casual. Use a 4-layer stackup minimum with a dedicated GND reference plane adjacent to the DP pairs.
• No HDMI 2.1 / 8K. PS176 caps at HDMI 2.0 / 4K@60. For future 8K@60 support you'd need PS195/PS196 (DP 2.0 → HDMI 2.1) — different chips, different pinout, higher cost.
• No HBR3 support on PS176. DP input accepts DP 1.3/1.4 format but only at HBR2 rates. For 5K or 4K@120 you'd need a different chip. Not relevant for this design.
• Internal SPI ROM vs external flash ambiguity in datasheet — see SPI ROM section. Default assumption: use internal ROM, leave external flash footprint DNP.
• Audio sample rate ceiling 192 kHz. Plenty for any realistic use. Modern ultra-hi-res audio (PCM above 192 kHz, DSD) doesn't pass through.
• Parade's "Do Not Distribute Without Permission" watermark on the datasheet — the datasheet is technically NDA-covered, though widely available through LCSC and Chinese distributors. For a commercial product, request an official datasheet from Parade directly via sales@paradetech.com.

Pairing with the retro VGA port

This main HDMI output (PS176-based) and the retro VGA port (AG6201-based) coexist on the same board and serve different audiences:

The FPGA can drive both simultaneously with different content — e.g., a debug OSD or native-resolution rendering on the main HDMI for the developer, while the retro port shows the clean 240p-superresolution signal to a SCART CRT for authentic-look gameplay.

Links

• Parade PS176 product page — official marketing / key features.
• PS176 datasheet on LCSC — technically NDA but widely available.
• LCSC product listing — stock + pricing reference.
• rgb_out — sibling doc for the retro VGA + audio port (AG6201-based).