Duo - Main Processing Unit

This is a MilkV Duo 256 (SG2002 microcontroller), it has 256MB RAM, it has 700Mhz RiscV core and either a 1Ghz RiscV core or a 1Ghz Arm Cortex A53 core, a 25 to 300Mhz 8051 core and a 1 TOPS Tensor unit (TPU). The Ant64 will operate it in RiscV mode. Audio will also go directly from/to the “Jazz” chip.

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The TF card interface (SPI0?) will go to the DeMon chip, which will act as an SD card emulator.

SD1 will go direct to...

Pins 21 to 27 (can be configured as a QSPI NOR Flash interface – they will go direct to the Razz. This way the CPU can communicate with the Razz “gpu” as if it was memory mapped IO.

Duo provides a 100MBPS network port.

The Duo has a fast USB interface.

Slower interfaces will go to the Debug monitor, input controller, audio synthesizer and optional “Network controller”.

The current plan is to have the 700Mhz RiscV core provide the operating system, housekeeping tasks, the “monitor” and the built-in computer languages (BASIC/Action). The 1Ghz RiscV core will provide emulation of various processors to simulate various 8 and 16 bit systems.

When emulating a computer, for example an Amiga A1200. The memory inside the MilkV Duo will be used rather than memory available to the "Razz" chip.

An amiga A1200 has a max memory bandwidth of 28MBytes/sec = 224mbits/sec (a normal amiga is 7Mbytes/sec = 56mbit/sec). With RAM being available to the emulated CPU all the time, it will mean the cpu will emulate as fast as possible.

The simulated GPU in the FPGA will request memory via the MilkV Duo MIPI RX port – which can operate at up to 1.5Gbit/sec and then transmit the requested data through the MIPI TX port – which can operate at up to 2.5Gbit.

There will be a protocol to read from “chip registers” contained in the FPGA by requesting them from the TX port and waiting for them at the RX port.

FRAM256 map (0000000-FFFFFFF)

Start address End address Size Description
000000003FFFFF04000004MB SRAM
040000007FFFFF0400000Reserved
08000000FFFFFF0C00000Reserved
8000000FFFFFFF8000000128MB SDRAM

Duo pinouts:

Pin Description CPU pin Function
1GP0 - JTAG TDI 28WTDI / XGPIOA 28
2GP1 - JTAG TDO 29WTDO / XGPIOA 29
3GND
4GP2 - JTAG TMS 26WTMS / XGPIOA 19
5GP3 - JTAG TCK 27WTCK / XGPIOA 18
6GP4 - SD1_D2 - SPINOR1_WP 52SD1 D2
7GP5 - SD1_D1 - SPINOR1_HOLD 53SD1 D1
8GND
9GP6 - SD1_CLK - SPINOR1_SCK 56SD1 CLK
10GP7 - SD1_CMD - SPINOR1_MOSI 55SD1 CMD
11GP8 - SD1_D0 - SPINOR1_MISO 54SD1 D0
12GP9 - SD1_D3 - SPINOR1_CS 51SD1 D3
13GND
14GP10 - I2C1 SDA - Razz slave 85Originally 1.8v, now 3.3v (see J1 pin 13)
15GP11 - I2C1 SCL - Razz slave 86Originally 1.8v, now 3.3v (see J1 pin 14)
16GP12 - UART0 TX - to Jazz 18UART0 TX / XGPIOA 16 – connected via 4.7k resistor to 3.3v
17GP13 - UART0 RX - from DeMon 19UART0 RX / XGPIOA 17 – connected via 4.7k resistor to 3.3v
18GND
19GP14 – used for SPI (SD0) slave select? 15SD0_PWR / XGPIOA 14 (See SD CARD interface!)
20GP15 – used for SPI (SD0) slave select? 17SPK_EN / XGPIOA 15
Pin Description CPU pin Function
40VBUS
39VSYS
38GND
373v3 EN
363v3 OUT
35Boot switch (1.8v?) 67GPIO_RTX / XGPIOB 23 – connected via 4.7k resistor to 1.8v
34Audio out (1.8v?) 4PAD_AUD_AOUTR / XGPIOC 24
33GND
32GP27 (1.8v) ADC1 - VSync interrupt via 3.3v conv60ADC2 / XGPIOB 6 / USB_VBUS_DET
31GP26 (1.8v) ADC0 - HSync interrupt via 3.3v conv59ADC1 / XGPIOB 3
30RUN 38(originally 1.8v, now 3.3v?)
29GP22 - Pixel clock input 41(originally 1.8v, now 3.3v) PWR_GPIO 4
28GND
27GP21 - SPINOR_HOLD – NOR interface to Jazz? 20SPINOR_HOLD / XGPIOA 26
26GP20 - SPINOR_WP 23SPINOR_WP / XGPIOA 27
25GP19 - SPINOR_MOSI 22SPINOR_MOSI / XGPIOA 25
24GP18 - SPINOR_SCK 21SPINOR_SCK / XGPIOA 22
23GND
22GP17 - SPINOR_CS 25SPINOR_CS / XGPIOA 24
21GP16 - SPINOR_MISO 24SPINOR_MISO / XGPIOA 23
  • LED is GP25 is CPU 49 (1.8v? PWR_GPIO 2)
  • DBG 12 is CPU pin 30 (XGPIOA 30) – To GND via 4.7k resistor
  • MIC is CPU pin 2 (PAD_AUD_AINL / XGPIOC 23) 1.8v?
  • USB pinouts:

    Pin Description CPU pin
    USB DP69
    USB DM70

    Ethernet pinouts:

    Pin Description CPU pin Function
    1RXN62XGPIOB 25
    2RXP63XGPIOB 24
    3GND
    4TXN64XGPIOB 27
    5TXP65XGPIOB 26

    SD card pinouts:

    SDCard Description SPI Master CPU pin Function
    4VDD 3.3v
    5CLKSPI0 SCK 6SD0 CLK / XGPIOA 7
    3CMDSPI0 SDO (MOSI) 7SD0 CMD / XGPIOA 8
    7D0SPI0 SDI (MISO) 83.3v
    8D1 10C
    1D2 11SD0 D2 / XGPIOA 11
    2D3SPIO CS 12SD0 D3 / XGPIOA 12
    CDSwitch DETSPIO CS 14C
    On Milk V 256M pin 19 15SD0 PWR EN / XGPIOA 14

    J1 (camera) pinouts:

    Pin Description CPU pin CPU Description (All 1.8v only)
    1GND GND
    2MIPI0_DN0 – from Razz 80PAD_MIPI RX0N / XGPIOC 10
    3MIPI0_DP0 – from Razz 81PAD_MIPI RX0P / XGPIOC 11/td>
    4GND GND
    5MIPI0_DN1 – from Razz 76PAD_MIPI RX2N / XGPIOC 6
    6MIPI0_DP1 – from Razz 77PAD_MIPI RX2P / XGPIOC 7
    7GND GND
    8MIPI0_CKN – from Jazz 78PAD_MIPI RX1N / XGPIOC 8
    9MIPI0_CKP – from Jazz 79PAD_MIPI RX1P / XGPIOC 9
    10GND GND
    11SENSOR_RSTN (1.8V) 84XGPIOC 17
    12SENSOR_CLK (1.8V) 88XGPIOC 15
    13I2C2_SCL (1.8V) 85XGPIOC 14 / I2C 2 SDA (See main pin 14)
    14I2C2_SDA (1.8V) 86XGPIOC 15 / I2C 2 SCL (See main pin 15)
    15 NC
    163V3

    Important: The Ant32 and Ant64 are both still at early design and prototype stage, everything you see here is subject to change.