FireStorm — FPGA

FireStorm is not a fixed "sound chip" or a simple video controller — it is a reconfigurable, multi-paradigm execution fabric at the heart of the Ant64.

Overview

FireStorm is built around the GoWin GW5AT-LV138Pg484A FPGA. It handles screen generation, audio DSP, 2D rasterisation, and high-speed memory access — all simultaneously.

  • Reads a special display program to generate the screen layout and HDMI video signal
  • Combined with a WM8958 or WM8960 codec for audio I/O + optical digital audio out
  • Runs various hardware emulators — Amiga, Atari STE, SNES, NES, C64, VIC-20, PacMan, Spectrum, MSX2 / Yamaha VDP

Memory

  • 1 or 2GB DDR3 SDRAM — 256/512M words × 32-bit (direct FPGA access)
  • 9MB fast SRAM — 2 independent banks of 1M words × 36-bit

Security

The FPGA supports both 128-bit AES encrypted and unencrypted bitstream images. The key is stored in a locked, write-once secure location — once set it cannot be read or overwritten. This allows encrypted personality cartridges whilst still permitting unencrypted community images.

The AES key will be set before distribution — if not set first, anyone could lock it with their own key.

DeMon programs FireStorm via JTAG at boot, and can display a logo or effect from its own flash whilst the rest of the system initialises.

FPGA Comparison

Feature Ant64s/Ant64b Ant64/Ant64c Next (KS1) Next (KS2) Next (KS3)
Device GW5A-60 GW5A-138 XC6LX9 XC7A15T XC7A35T
LUT4 59,904 138,240 9,152 16,640 33,380
Shadow SRAM (Kbits) 468 1,080 90 200 400
Block SRAM (Kbits) 2,124 6,120 576 900 1,800
Number of BSRAM 118 340 ?? 25 50
DSP multipliers 118 298 16 45 90

JTAG

Signal Lines

Signal Direction Description
TCK Out Clock — connected to all devices
TMS Out Mode select — connected to all devices
TDI Out Data in — chained from previous device TDO
TDO In Data out — last device in chain

Status Pins

  • READY
  • CONFIG
  • DONE

On the Tang Primer 25K, the debug test points are the JTAG lines.

FRAM Interfaces

The main chips — SG2000, DeMon, QMK, and Pulse — interface to FireStorm via a FRAM (Fake QSPI RAM) interface. Hosts map this directly into their memory space:

  • All chips get 4GB mapped shared access to FireStorm's DDR3/SRAM
  • Each FRAM16 interface leaves 12MB spare per chip in the memory map
  • The SG2000's FRAM256 interface leaves 252MB spare

Audio Codec

The WM8958 or WM8960 codec is wired to an I2S output, with I2C controlled by Pulse. The DAC drives:

  • Headphone / microphone connection
  • 2× internal speakers
  • Audio sampler connections
  • SG2000 audio out (possibly stereo)

The SG2000 has a microphone input connected to the internal motherboard mic. Its Tensor unit can be used for voice recognition, with mono audio output fed into R3/L3 for mixing.

WM8958 — I/O Routing

Input Source Output Destination
L1 (in1) Headphone microphone (mono) LHP (2nd DAC) Headphone L — 5.3mW
R1 (in1) — RHP (2nd DAC) Headphone R
L2 (in1) LSAM — Sampler left LSPK (1st DAC) L internal speaker — 2W
R2 (in1) RSAM — Sampler right RSPK (1st DAC) R internal speaker
L3 (in2) SG2000 audio out (mono?) L line out 1 —
R3 (in2) SG2000 audio out (mono?) R line out 1 —
L4 (in2) — L line out 2 —
R4 (in2) — R line out 2 —

AIF1 is connected directly to FireStorm.

WM8960 — I/O Routing

Input Source Output Destination
L1 Headphone microphone (mono) LHP Headphone socket L
R1 — RHP Headphone socket R
L2 LSAM — sampler socket left LSPK Left internal speaker
R2 RSAM — sampler socket right RSPK Right internal speaker
L3 SG2000 audio out (mono?) — —
R3 SG2000 audio out (mono?) — —

Prototype 1 — Tang Primer 25K

Prototype 1 features: HDMI out · 64MB 5ns SDRAM · 8MB QSPI NOR Flash · SG2000 FRAM256 interface · I2S raw audio from Pulse · VSync out · HSync out · Pixel clock out · Pulse Sequencer SPI master · I2C system master (all chips)

J3 — SDRAM

RAM Function Pin Pin Function RAM
D0 K2 IOR20B 1 2 K1 IOR20A D1
D2 L1 IOR18B 3 4 L2 IOR18A D3
D4 K4 IOR22B 5 6 J4 IOR22A D5
D6 G1 IOR24B 7 8 G2 IOR24A D7
D15 L3 IOR31B 9 10 L4 IOR31A D14
+V 5V 11 12 GND GND
D13 C2 IOB04B 13 14 B2 IOB4A D12
D11 F1 IOB26B 15 16 F2 IOB26A D10
D9 A1 IOB24A 17 18 E1 IOB12B D8
A12 D1 IOB14B 19 20 E3 IOB60A CLK
A9 J2 IOR33B 21 22 J1 IOB33A A11
A7 H4 IOB89B 23 24 G4 IOB89A A8
A5 H2 IOB91B 25 26 H1 IOB91A A6
WE J7 IOT21B 27 28 K7 IOT21A A4
LDM L8 IOT19B 29 30 L7 IOT19A UDM
CAS K10 IOT15B 31 32 L10 IOT15A RAS
CS0 K9 IOT31B 33 34 L9 IOT31A BA0
BA1 K8 IOT56B 35 36 J8 IOT56A A10
A0 F6 IOT58B 37 38 F7 IOT58A A1
A2 J10 IOT1B 39 40 J11 IOT1A A3

J4

Pin FPGA Description Pin FPGA Description
2 3v3 1 3v3
4 GND 3 GND
6 C10 IOL5B SG2000 memory WP 5 C11 IOL5A SG2000 memory HOLD
8 B10 IOL12B SG2000 memory MOSI 7 B11 IOL12A SG2000 memory MISO
10 D10 IOL9B SG2000 memory SCK 9 D11 IOL9A SG2000 memory CS
12 G10 IOT7B I2S PCM1808 BCK 11 G11 IOT7A I2S PCM1808 DATA
8 L11 IOT11B SPI master MISO 7 K11 IOT11A SPI master MOSI
10 E10 IOL3B SPI master SCK 9 E11 IOL3A SPI master CS0 — Pulse Sequencer
12 A10 IOL14B I2C master SCL 11 A11 IOL14A I2C master SDA

J5

Pin FPGA Description Pin FPGA Description
2 3v3 1 3v3
4 GND 3 GND
6 K5 IOT63B I2S PCM1808 LRCK 5 L5 IOT63A Pixel clock out

J6 — HDMI

Pin FPGA Description Pin FPGA Description
2 3v3 1 3v3
4 GND 3 GND
6 J5 IOT61B HDMI CKN — CTRL/STATUS 5 H5 IOT61A HDMI CKP — CTRL/STATUS
8 H7 IOT66B HDMI D0N — BLUE, H/V SYNC 7 H8 IOT66A HDMI D0P — BLUE, H/V SYNC
10 G8 IOT68B HDMI D1N — GREEN, CTL 0/1 9 G7 IOT68A HDMI D1P — GREEN, CTL 0/1
12 G5 IOT72B HDMI D2N — RED, CTL 2/3 11 F5 IOT72A HDMI D2P — RED, CTL 2/3

USB A Host

Pin FPGA Description
1 L6 IOT23A USB-A P — VSync out
2 K6 IOT23B USB-A N — HSync out
3 E8 READY USB DP Pull

Debug

Pin FPGA Description
1 B1 JTAG TMS JTAG TMS
2 A3 JTAG TDI JTAG TDI
3 C1 JTAG TCK JTAG TCK — 5.1k resistor to GND
4 — 5V
5 A2 JTAG TDO JTAG TDO
6 — GND
7 — 3v3
8 — BL616 Enable — connect to GND to disable BL616
— B3 IOB56A UART TX — to BL616 UART RX
— C3 IOB56B UART RX — to BL616 UART TX

LED

Pin FPGA Description
3 E8 READY Ready = 1, not ready = 0
4 D7 DONE Done = 1, fail = 0

Button

Pin FPGA Description
1 H11 IOT3A S1
2 H10 IOT3B S2

4-Pin Connector

Pin FPGA Description
1 D8 Reconfig —
2 GND —
3 E8 Ready —
4 D7 Done —

Special Pins

Pin Default Description
IOB01A RECONFIG_N Global reset for GowinCONFIG logic — active low
IOB33B EMCCLK Optional external clock input for master mode configuration. Ignored in JTAG/slave modes.
IOB37A READY High = device can be programmed; Low = device cannot be programmed
IOB37B MCS_N/CSO_B MSPI mode: enable signal, active-low
IOB52A MODE1 Set to 0 via resistor — Master mode, FPGA reads config from external Flash via SPI
IOB54A MI2 MSPI X4 mode: parallel data bit 2 — connects to DQ2/WP#/IO2 of external Flash
IOB54B MI3 MSPI X4 mode: parallel data bit 3 — connects to DQ3/HOLD#/IO3 of external Flash
IOB58A MISO MSPI X1: serial data input. X2/X4: parallel data bit 1 — connects to DQ1/SO/IO1
IOB58B MOSI MSPI: serial instruction/address output. X2/X4: parallel data bit 0 — connects to DQ0/SI/IO0
IOB62A CCLK Slave mode: clock input from external source. Master mode: clock output
IOB62B MODE0 Set to 1 via resistor — Master mode, FPGA reads config from external Flash via SPI
IOB64A DONE Input: low = delay activation until high. Output: high = config complete; low = config failed or incomplete
IOR01A TCK JTAG: serial clock input
IOR01B TDI JTAG: serial data input
IOR03A TMS JTAG: serial mode input
IOR03B TDO JTAG: serial data output
IOT29A PUDC_B Active-low weak pull-up selection during configuration. Low = all GPIOs weak pull-up; High = all GPIOs high impedance. Must not be left floating.

Reference Links

Important: The Ant64 family of home computers are at early design/prototype stage, everything you see here is subject to change.