eZX

The eZX is one of the Ant64's FPGA personalities: a modern re-imagining of the ZX Spectrum built on an enhanced 32-bit RISC-V soft core. It shares the Ant64's execution-engine DNA — the same custom instruction families — scaled to RV32, with one extension of its own (Xez) for Z80 ergonomics. This page is the overview and hub; the CPU detail lives in the reference docs.

Note: overview/hub page. The authoritative CPU material is cpu (overview) and cpu_reference (Xez, CSRs, traps). Hardware, chipset, and memory-map specifics live in the eZX spec and chipset docs.

Related: the full Ant64 machine → FireStorm / ee_cpu. The console BASIC that can target this core → AntBASIC.

What the eZX is

The eZX runs on the same GoWin FPGA as the full Ant64 machine, but as a different loaded image — a Spectrum-lineage personality rather than the full FireStorm machine. Where the Ant64's EE is an enhanced RV64 core, the eZX is an enhanced RV32 core: standard RISC-V at its base, so any RV32 toolchain can target it, with a stack of custom extensions on top.

AntOS still runs on the DeMon supervisor (the CM4/5) alongside the eZX, brokering storage, syscalls, and the mailbox interface; the eZX itself runs the guest software.

The core in one table

Aspect eZX
Base ISA RV32 — RV32IMFC_Zicsr_Zifencei_Zbb_Zbs_Zicond (see cpu for the exact profile)
Custom extensions (shared with the EE) Xcrisp, Xmath, Xstack, Xlate, Xctx, Xcond, Xwide
Custom extension (eZX-only) Xez — Z80-ergonomics: an ezflags register, flag-setting arithmetic, conditional/decrement branches, single-bit memory tests (cpu_reference)
Encoding narrow (32-bit) or wide (36-bit slot) — see below
Pipeline single-issue, in-order, 5-stage, with prefetch buffer + speculative load run-ahead + write FIFO (cpu)

The shared families mean an Ant64 game developer can recompile FireStorm code (in its narrow RV32 form) and have it run on the eZX with the same Xcrisp/Xmath/Xstack/Xlate/Xctx encoding — the two cores are close relatives, one RV32 and one RV64.

Narrow and wide, by memory location

Like the EE, the eZX runs instructions in one of two encodings, chosen by where the code lives — independent of the RV32 base:

Encoding Slot Gains Memory
Narrow standard 32-bit RISC-V the baseline HyperRAM (16 MB, always present), FPGA flash (boot/mini-OS)
Wide 36-bit = 32-bit instruction + a 4-bit Xwide nibble 64 GPRs + 64 FPRs, wider immediates, per-instruction predication (Xcond) DDR3 (72-bit, two 36-bit slots per word) and SRAM

All-zero-nibble wide code is bit-identical to narrow, so narrow is the baseline and wide is the strict superset. On the eZX, DDR3 is the optional SODIMM, so wide mode depends on it being fitted; without it the eZX runs entirely narrow from HyperRAM. See ezx_xwide for the mode-selection rules.

Relationship to the Ant64 / EE

The eZX and the Ant64's EE (FireStorm) are deliberately parallel designs:

  • Shared extension families — Xcrisp, Xmath, Xstack, Xlate, Xctx, Xcond, Xwide encode identically on both.
  • The cross-compatible profile is RV32 narrow — code written to it runs on the eZX and on the EE (whose RV64 base is a superset).
  • Differences — the EE is RV64 (64-bit ops, *w word instructions, ld/sd); the eZX is RV32 and adds Xez for Z80-style code. Each core's exclusive opcodes error on the other.

Targeting the eZX from AntBASIC

The AntOS console's AntBASIC can hand-assemble RISC-V for whichever core the FPGA is currently being. Under the eZX image, the { … } inline RISC-V assembler assembles RV32 for the eZX core (narrow or wide by target memory), and a fully-assembly program can be exported as a standalone .ezx executable — a header plus an absolute-addressed image the AntOS loader places in FPGA memory and runs on the eZX. See AntBASIC → building executables.

Where to go next

Important: The Ant64 family of home computers are at early design/prototype stage, everything you see here is subject to change.